Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
384
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
34:32
RWS
0x0
showportid:
A Port Identifier that identifies which PCI Express port a transaction comes 
from will be placed in the AD Ring TNID[2:0] field of the request packet, 
when enabled. This field is normally used for DCAHint and is not used for 
normal demand read.
Since there are up to 11 specific ports, then Port ID is encoded in 4 bits. 
Only three bits can be selected to be sent in TNID as follows:
100: TNID[2:0] = PortID[3:1]
011: TNID[2:0] = PortID[3:2, 0]
010: TNID[2:0] = PortID[3, 1:0]
001: TNID[2:0] = PortID[2:0]
000: IIO will not send Port ID information in the TNID[2:0] field
The PortIDs are mapped as follows:
0: Device 0 Function 0 DMI/PCIe* port 0 (IOU2)
1: Unused
2: Unused
3: Device 2 Function 0 Port 2a x4, x8, or x16 (IOU0)
4: Device 2 Function 1 Port 2b x4 (IOU0)
5: Device 2 Function 2 Port 2c x4 or x8 (IOU0)
6: Device 2 Function 3 Port 2d x4 (IOU0)
7: Device 3 Function 0 Port 3a x4, x8, or x16 or NTB port x4 or x8 (IOU1)
8: Device 3 Function 1 Port 3b x4 (IOU1)
9: Device 3 Function 2 Port 3c x4 or x8 (IOU1)
10: Device 3 Function 3 Port 3d x4 (IOU1)
11: Intel® Quick Data
12: Intel
®
VT
Notes:
The TNID[2:0] value will be copied to the TORID[4:0] by CBo, if the packet 
is to be sent to the Intel
®
QPI port.
31:31
RV
-
Reserved.
30:30
RW
0x1
treat_last_write_in_descriptor_specially:
Treat Intel® Quick Data DMA writes with NS = RO = 1  NS is enabled in 
Intel® Quick Data DMA  'last write in descriptor', as-if NS = 1 and RO = 0 
write
29:26
RV
-
Reserved.
25:25
RWS
0x1
cballocen:
When set, use Allocating Flows for non-DCA writes from Intel® Quick Data 
DMA. This bit does not affect DCA requests when DCA requests are enabled 
(bit 21 of this register). A DCA request is identified as matching the DCA 
requestor ID and having a Tag of non-zero. All DCA requests are always 
allocating, unless they are disabled, or unless all allocating flows are 
disabled (bit 24). If all allocating flows are disabled, then DCA requests are 
also disabled.
BIOS is to leave this bit at default of 1b for all but DMI port. See the 
transaction flow chapter for when non-snoop can be enabled from Intel® 
Quick Data DMA and its relationship to the setting of this bit.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x1c0
Bit
Attr
Default
Description
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