Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
467
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.8.50 IIOERRST
IIO Core Error Status.
This register indicates the IIO internal core errors detected by the IIO error logic. An 
individual error status bit that is set indicates that a particular error occurred; software 
may clear an error status by writing a 1 to the respective bit. This register is sticky and 
can only be reset by PWRGOOD. Clearing of the IIO**ERRST is done by clearing the 
corresponding IIOERRST bits.
14.8.51 IIOERRCTL
IIO Core Error Control.
This register controls the reporting of IIO internal core errors detected by the IIO error 
logic. An individual error control bit that is cleared masks reporting of that a particular 
error; software may set or clear the respective bit. This register is sticky and can only 
be reset by PWRGOOD.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5
Function:
2
Offset:
0x300
Bit
Attr
Default
Description
31:7
RV
-
Reserved3:
Reserved.
6:6
RW1CS
0x0
c6:
C6 Error Status. (Overflow/Underflow)
5:5
RV
-
Reserved2:
Reserved
4:4
RW1CS
0x0
c4:
C4 Error Status. (Master Abort)
3:0
RV
-
Reserved1:
Reserved.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5
Function:
2
Offset:
0x304
Bit
Attr
Default
Description
31:10
RV
-
Reserved.
9:9
RWS_L
0x0
c4_viral_disable:
Disables logging C4 error and PCIe* UR in VIRAL state when set to one.
Notes: Locked by RSPLCK
Disabling C4 error logging is dependent on viral state being asserted not viral 
status. It is recommended that traffic towards the IIO be quiesced before 
clearing the viral state to avoid a race condition between clearing the register 
bit and the IIO exiting Viral.
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