Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
485
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.9.20 PMCAP
Power Management Capabilities.
14.9.21 PMCSR
Power Management Control and Status.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0xe0
Bit
Attr
Default
Description
31:27
RO
0x0
pme_support:
Bits 31, 30 and 27 must be ‘0’. PME is not supported in this device/function.
26:26
RO
0x0
d2_support:
I/OxAPIC does not support power management state D2
25:25
RO
0x0
d1_support:
I/OxAPIC does not support power management state D1
24:22
RO
0x0
aux_current:
21:21
RO
0x0
device_specific_initalization:
20:20
RV
-
Reserved.
19:19
RO
0x0
pme_clock:
This field is hardwired to 0h as it does not apply to PCI Express. 
18:16
RW_O
0x3
version:
This field is set to 3h (PM 1.2 compliant) as version number. Bit is RW_O to 
make the version 2h incase legacy OS’es have any issues.
15:8
RO
0x0
next_pointer:
This is the last capability in the chain and hence set to 0. 
7:0
RO
0x1
capability_id:
Provides the PM capability ID assigned by PCI-SIG.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0xe4
Bit
Attr
Default
Description
31:24
RO
0x0
data:
Not relevant for I/OxAPIC
23:23
RO
0x0
bpcce:
Not relevant for I/OxAPIC
22:22
RO
0x0
b2b3:
Not relevant for I/OxAPIC
21:16
RV
-
Reserved.
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