Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
483
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.9.17 SNAPSHOT_INDEX
14.9.18 SNAPSHOT_WINDOW
19:16
RO
0x1
capability_version:
PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec.
Note:
This capability structure is not compliant with Versions beyond 1.0, since 
they require additional capability registers to be reserved. The only purpose 
for this capability structure is to make enhanced configuration space 
available. Minimizing the size of this structure is accomplished by reporting 
version 1.0 compliancy and reporting that this is an integrated root port 
device. As such, only three Dwords of configuration space are required for 
this structure.
15:8
RO
0xe0
next_ptr:
Pointer to the next capability. If set to 0 to indicate there are no more 
capability structures.
7:0
RO
0x10
capability_id:
Provides the PCI Express capability ID assigned by PCI-SIG.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x80
Bit
Attr
Default
Description
7:0
RW
0x0
ssidx:
When PECI/JTAG wants to read the indirect RTE registers of I/OxAPIC, this 
register is used to point to the index of the indirect register, as defined in the 
I/ OxAPIC indirect memory space. Software writes to this register and then 
does a read of the RDWINDOW register to read the contents at that 
index.Note h/w does not preclude software from accessing this register over 
the coherent interface but that is not what this register is defined for. 
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x90
Bit
Attr
Default
Description
31:0
RO_V
0x0
sswindow:
When SMBUS/JTAG reads this register, the data contained in the indirect 
register pointed to by the RDINDEX register is returned on the read. 
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:4
Offset:
0x44
Bit
Attr
Default
Description
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