Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
PCU - Universal Asynchronous Receiver/Transmitter (UART)
1080
Datasheet
21.7
PCU iLB UART IO Registers
21.7.1
Receiver Buffer / Transmitter Holding Register
(COM1_Rx_Tx_Buffer)—Offset 3F8h
This register is a combination of three registers: the receiver buffer register (RBR) that
is a read-only register when DLAB=0, the transmitter holding register (THR) that is a
write-only register when DLAB=0 and the divisor latch LSB (DLL) register when
DLAB=1.
Access Method
Default: 00h
Table 158.
Summary of PCU iLB UART
I/O Registers
Offset
Size
Register ID—Description
Default
Value
3F8h
1
00h
3F9h
1
00h
3FAh
1
01h
3FBh
1
00h
3FCh
1
00h
3FDh
1
60h
3FEh
1
00h
3FFh
1
00h
Type: I/O Register
(Size: 8 bits)
COM1_Rx_Tx_Buffer: 3F8h
7
4
0
0
0
0
0
0
0
0
0
RBR_THR_DLL