Intel J1850 User Manuals

Table of Contents

• Intel® Pentium® Processor N3500- series, J2850, J2900, and Intel® Celeron® Processor N2900-series, N2800-series, J1800-series, J1900, J1750

  1
• Revision History

  13
• 1 Introduction

  14
  • 1.1 Terminology

    16
  • 1.2 Feature Overview

    17
• 2 Physical Interfaces

  22
  • 2.1 Pin States Through Reset

    24
  • 2.2 System Memory Controller Interface Signals

    25
  • 2.3 PCI Express* 2.0 Interface Signals

    26
  • 2.4 USB 2.0 Host (EHCI/xHCI) Interface Signals

    26
  • 2.5 USB 2.0 HSIC Interface Signals

    27
  • 2.6 USB 3.0 (xHCI) Host Interface Signals

    27
  • 2.7 Serial ATA (SATA) 2.0 Interface Signals

    27
  • 2.8 Integrated Clock Interface Signals

    28
  • 2.9 Display – Digital Display Interface (DDI) Signals

    29
  • 2.10 Display – VGA Interface Signals

    30
  • 2.11 Intel® High Definition Audio Interface Signals

    30
  • 2.12 SPCU – iLB – Real Time Clock (RTC) Interface Signals

    31
  • 2.13 PCU – iLB – Low Pin Count (LPC) Bridge Interface Signals

    31
  • 2.14 PCU – Serial Peripheral Interface (SPI) Signals

    32
  • 2.15 PCU – System Management Bus (SMBus) Interface Signals

    32
  • 2.16 PCU – Power Management Controller (PMC) Interface Signals

    33
  • 2.17 JTAG and Debug Interface Signals

    33
  • 2.18 Miscellaneous Signals

    34
  • 2.19 GPIO Signals

    34
  • 2.20 Power And Ground Pins

    39
  • 2.21 Hardware Straps

    41
  • 2.22 Configurable IO – GPIO Multiplexing

    41
• 3 Register Access Methods

  42
  • 3.1 Fixed IO Register Access

    42
  • 3.2 Fixed Memory Mapped Register Access

    42
  • 3.3 IO Referenced Register Access

    42
  • 3.4 Memory Referenced Register Access

    43
  • 3.5 PCI Configuration Register Access

    43
  • 3.6 Message Bus Register Access

    45
  • 3.7 Register Field Access Types

    46
• 4 Mapping Address Spaces

  48
  • 4.1 Physical Address Space Mappings

    48
  • 4.2 IO Address Space

    53
  • 4.3 PCI Configuration Space

    55
• 5 Integrated Clock

  57
  • 5.1 Features

    58
• 6 Power Management

  60
  • 6.1 Power Management Features

    60
  • 6.2 Power Management States Supported

    60
  • 6.3 Processor Core Power Management

    64
  • 6.4 Memory Controller Power Management

    70
  • 6.5 PCI Express* (PCIe*) Power Management

    72
• 7 Thermal Management

  73
  • 7.1 Overview

    73
  • 7.2 Thermal Design Power (TDP)

    73
  • 7.3 Scenario Design Power (SDP)

    74
  • 7.4 Thermal Sensors

    74
  • 7.5 Hardware Trips

    75
  • 7.6 Processor Programmable Trips

    75
  • 7.7 Platform Trips

    76
  • 7.8 Thermal Throttling Mechanisms

    76
  • 7.9 Thermal Status

    76
• 8 Electrical Specifications

  77
  • 8.1 Thermal Specifications

    77
  • 8.2 Storage Conditions

    78
  • 8.3 Voltage and Current Specifications

    79
  • 8.4 Crystal Specifications

    88
  • 8.5 DC Specifications

    90
• 9 Package Information

  106
  • 9.1 Processor Attributes

    106
  • 9.2 Package Diagrams

    107
• 10 Processor Core

  108
  • 10.1 Features

    108
  • 10.2 Platform Identification and CPUID

    111
  • 10.3 References

    111
  • 10.4 System Memory Controller

    112
  • 10.5 Signal Descriptions

    112
  • 10.6 Features

    114
• 11 Processor Transaction Router

  117
  • 11.1 Transaction Router C-Unit PCI Configuration Registers

    118
• 12 Graphics, Video, and Display

  122
  • 12.1 Features

    122
  • 12.2 Processor Graphics Display

    123
  • 12.3 Display Pipes

    124
  • 12.4 Display Physical Interfaces

    124
  • 12.5 References

    130
  • 12.6 3D Graphics and Video

    130
  • 12.7 Features

    131
  • 12.8 VED (Video Encode/Decode)

    133
• 13 Serial ATA (SATA)

  134
  • 13.1 Signal Descriptions

    134
  • 13.2 Features

    135
  • 13.3 References

    137
  • 13.4 Register Map

    138
  • 13.5 SATA PCI Configuration Registers

    139
  • 13.6 SATA Legacy IO Registers

    171
  • 13.7 SATA Index Pair IO Registers

    177
  • 13.8 SATA AHCI Memory Mapped IO Registers

    179
  • 13.9 SATA Primary Read Command IO Registers

    218
  • 13.10 SATA Primary Write Command IO Registers

    223
  • 13.11 SATA Primary Read Control IO Registers

    225
  • 13.12 SATA Primary Write Control IO Registers

    226
  • 13.13 SATA Secondary Read Command IO Registers

    227
  • 13.14 SATA Secondary Write Command IO Registers

    232
  • 13.15 SATA Secondary Read Control IO Registers

    234
  • 13.16 SATA Secondary Write Control IO Registers

    235
  • 13.17 SATA Lane 0 Electrical Register Address Map

    236
  • 13.18 SATA Lane 0 Electrical Register Address Map

    269
  • 13.19 SATA Lane 1 Electrical Register Address Map

    286
  • 13.20 SATA Lane 1 Electrical Register Address Map

    320
• 14 USB Host Controller Interfaces (xHCI, EHCI)

  337
  • 14.1 Signal Descriptions

    337
  • 14.2 USB 3.0 xHCI (Extensible Host Controller Interface)

    339
  • 14.3 USB 2.0 Enhanced Host Controller Interface (EHCI)

    340
  • 14.4 References

    341
  • 14.5 Register Map

    342
  • 14.6 USB xHCI PCI Configuration Registers

    343
  • 14.7 USB xHCI Memory Mapped I/O Registers

    380
• 15 Intel® High Definition Audio (Intel® HD Audio)

  538
  • 15.1 Signal Descriptions

    539
  • 15.2 Features

    540
  • 15.3 References

    540
  • 15.4 Register Map

    541
  • 15.5 HD Audio PCI Configuration Registers

    542
  • 15.6 HD Audio Memory Mapped I/O Registers

    575
• 16 Intel® Trusted Execution Engine (Intel® TXE)

  697
  • 16.1 Features

    697
• 17 PCI Express* 2.0

  699
  • 17.1 Signal Descriptions

    699
  • 17.2 Features

    700
  • 17.3 References

    703
  • 17.4 Register Map

    703
  • 17.5 PCI Configuration Registers

    704
  • 17.6 PCI Express* PCI Configuration Registers

    705
  • 17.7 PCI Express* Lane 0 Electrical Address Map

    752
  • 17.8 PCI Express* Lane 0 Electrical Address Map

    784
  • 17.9 PCI Express* Lane 1 Electrical Address Map

    801
  • 17.10 PCI Express* Lane 1 Electrical Address Map

    832
  • 17.11 PCI Express* Lane 2 Electrical Address Map

    849
  • 17.12 PCI Express* Lane 2 Electrical Address Map

    880
  • 17.13 PCI Express* Lane 3 Electrical Address Map

    897
  • 17.14 PCI Express* Lane 3 Electrical Address Map

    928
• 18 Platform Controller Unit (PCU) Overview

  945
  • 18.1 Features

    945
  • 18.2 PCU iLB LPC Port 80h I/O Registers

    948
• 19 PCU – Power Management Controller (PMC)

  957
  • 19.1 Signal Descriptions

    957
  • 19.2 Features

    959
  • 19.3 USB Per-Port Register Write Control

    966
  • 19.4 References

    967
  • 19.5 PCU PMC Memory Mapped I/O Registers

    968
  • 19.6 PCU PMC IO Registers

    1002
  • 19.7 PCU iLB PMC I/O Registers

    1005
• 20 PCU – Serial Peripheral Interface (SPI)

  1023
  • 20.1 Signal Descriptions

    1023
  • 20.2 Features

    1024
  • 20.3 Use

    1037
  • 20.4 PCU SPI for Firmware Memory Mapped I/O Registers

    1039
• 21 PCU – Universal Asynchronous Receiver/Transmitter (UART)

  1075
  • 21.1 Signal Descriptions

    1075
  • 21.2 Features

    1076
  • 21.3 Use

    1078
  • 21.4 UART Enable/Disable

    1078
  • 21.5 Register Map

    1079
  • 21.6 IO Mapped Registers

    1079
  • 21.7 PCU iLB UART IO Registers

    1080
• 22 PCU – System Management Bus (SMBus)

  1089
  • 22.1 Signal Descriptions

    1089
  • 22.2 Features

    1090
  • 22.3 Use

    1096
  • 22.4 References

    1097
  • 22.5 Register Map

    1097
  • 22.6 PCU SMBus PCI Configuration Registers

    1099
  • 22.7 PCU SMBus Memory Mapped I/O Registers

    1114
  • 22.8 PCU SMBus I/O Registers

    1125
• 23 PCU – Intel® Legacy Block (iLB) Overview

  1138
  • 23.1 Signal Descriptions

    1138
  • 23.2 Features

    1139
  • 23.3 PCU iLB Interrupt Decode and Route

    1141
• 24 PCU – iLB – Low Pin Count (LPC) Bridge

  1180
  • 24.1 Signal Descriptions

    1180
  • 24.2 Features

    1181
  • 24.3 Use

    1186
  • 24.4 References

    1187
  • 24.5 Register Map

    1187
  • 24.6 PCU iLB Low Pin Count (LPC) Bridge PCI Configuration Registers

    1189
  • 24.7 PCU iLB LPC BIOS Control Memory Mapped I/O Registers

    1209
• 25 PCU – iLB – Real Time Clock (RTC)

  1210
  • 25.1 Signal Descriptions

    1210
  • 25.2 Features

    1211
  • 25.3 Interrupts

    1212
  • 25.4 References

    1213
  • 25.5 Register Map

    1213
  • 25.6 IO Mapped Registers

    1214
  • 25.7 Indexed Registers

    1214
  • 25.8 PCU iLB Real Time Clock (RTC) I/O Registers

    1216
• 26 PCU – iLB – 8254 Timers

  1218
  • 26.1 Signal Descriptions

    1218
  • 26.2 Features

    1218
  • 26.3 Use

    1219
  • 26.4 Register Map

    1222
  • 26.5 IO Mapped Registers

    1222
  • 26.6 PCU iLB 8254 Timers IO Registers

    1223
• 27 PCU – iLB – High Precision Event Timer (HPET)

  1229
  • 27.1 Features

    1229
  • 27.2 References

    1231
  • 27.3 Register Map

    1231
  • 27.4 Memory Mapped Registers

    1231
  • 27.5 PCU iLB High Performance Event Timer (HPET) Memory Mapped IO Registers

    1232
• 28 PCU – iLB – GPIO

  1241
  • 28.1 Signal Descriptions

    1241
  • 28.2 Features

    1241
  • 28.3 Use

    1242
  • 28.4 Register Map

    1243
  • 28.5 GPIO Registers

    1243
• 29 PCU – iLB – Interrupt Decoding and Routing

  1245
  • 29.1 Features

    1245
• 30 PCU – iLB – IO APIC

  1247
  • 30.1 Features

    1247
  • 30.2 Use

    1249
  • 30.3 References

    1249
  • 30.4 Indirect I/O APIC Registers

    1250
  • 30.5 PCU iLB IO APIC Memory Mapped I/O Registers

    1251
• 31 PCU – iLB – 8259 Programmable Interrupt Controllers (PIC)

  1253
  • 31.1 Features

    1253
  • 31.2 IO Mapped Registers

    1260
  • 31.3 PCU iLB 8259 Interrupt Controller (PIC) I/O Registers

    1262