Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
PCU – System Management Bus (SMBus)
1090
Datasheet
22.2
Features
22.2.1
Host Controller
The SMBus host controller is used to send commands to other SMBus slave devices.
Software sets up the host controller with an address, command, and, for writes, data
and optional PEC; and then tells the controller to start. When the controller has finished
transmitting data on writes, or receiving data on reads, it generates an SMI# or
interrupt, if enabled.
Software sets up the host controller with an address, command, and, for writes, data
and optional PEC; and then tells the controller to start. When the controller has finished
transmitting data on writes, or receiving data on reads, it generates an SMI# or
interrupt, if enabled.
The host controller supports 8 command protocols of the SMBus interface (see System
Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte,
Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write and
Block Write–Block Read Process Call.
Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte,
Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write and
Block Write–Block Read Process Call.
The SMBus host controller requires that the various data and command fields be setup
for the type of command to be sent. When software sets the START bit, the SMBus Host
controller performs the requested transaction, and interrupts the processor (or
generates an SMI#) when the transaction is completed. Once a START command has
been issued, the values of the “active registers” (Host Control (SMB_Mem_HCTL), Host
Command (SMB_Mem_HCMD), Transmit Slave Address (SMB_Mem_TSA), Data 0
(SMB_Mem_HD0), Data 1 (SMB_Mem_HD1)) should not be changed or read until the
interrupt status message (SMB_Mem_HSTS.INTR) has been set (indicating the
completion of the command). Any register values needed for computation purposes
should be saved prior to issuing of a new command, as the SMBus host controller
updates all registers while completing the new command.
for the type of command to be sent. When software sets the START bit, the SMBus Host
controller performs the requested transaction, and interrupts the processor (or
generates an SMI#) when the transaction is completed. Once a START command has
been issued, the values of the “active registers” (Host Control (SMB_Mem_HCTL), Host
Command (SMB_Mem_HCMD), Transmit Slave Address (SMB_Mem_TSA), Data 0
(SMB_Mem_HD0), Data 1 (SMB_Mem_HD1)) should not be changed or read until the
interrupt status message (SMB_Mem_HSTS.INTR) has been set (indicating the
completion of the command). Any register values needed for computation purposes
should be saved prior to issuing of a new command, as the SMBus host controller
updates all registers while completing the new command.
22.2.1.1
Command Protocols
In all of the following commands, the Host Status (SMB_Mem_HSTS) register is used to
determine the progress of the command. While the command is in operation, the
SMB_Mem_HSTS.HBSY bit is set. If the command completes successfully, the
SMB_Mem_HSTS.INTR bit will be set. If the device does not respond with an
acknowledge, and the transaction times out, the SMB_Mem_HSTS.DEVERR bit is set. If
software sets the SMB_Mem_HCTL.KILL bit while the command is running, the
transaction will stop and the SMB_Mem_HSTS.FAILED bit will be set.
determine the progress of the command. While the command is in operation, the
SMB_Mem_HSTS.HBSY bit is set. If the command completes successfully, the
SMB_Mem_HSTS.INTR bit will be set. If the device does not respond with an
acknowledge, and the transaction times out, the SMB_Mem_HSTS.DEVERR bit is set. If
software sets the SMB_Mem_HCTL.KILL bit while the command is running, the
transaction will stop and the SMB_Mem_HSTS.FAILED bit will be set.
Table 159. SMBus Signal Names
Signal Name
Direction
Type
Description
PCU_SMB_ALERT#
I/OD
CMOS1.8
SMBus Alert: This signal is used to generate internal SMI#.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
PCU_SMB_CLK
I/OD
CMOS1.8
SMBus Clock: External pull-up resistor is required.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
PCU_SMB_DATA
I/OD
CMOS1.8
SMBus Data: External pull-up resistor is required.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.