Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
111
Processor Core
10.1.3
Power Aware Interrupt Routing
PAIR is an improvement in H/W routing of “redirectable” interrupts. Each core power-
state is considered in the routing selection to reduce the power or performance impact
of interrupts. System BIOS configures the routing algorithm, e.g. fixed-priority,
rotating, hash, or PAIR, during setup via non-architectural register. The PAIR algorithm
can be biased to optimize for power or performance and the largest gains will be seen
in systems with high interrupt rates.
state is considered in the routing selection to reduce the power or performance impact
of interrupts. System BIOS configures the routing algorithm, e.g. fixed-priority,
rotating, hash, or PAIR, during setup via non-architectural register. The PAIR algorithm
can be biased to optimize for power or performance and the largest gains will be seen
in systems with high interrupt rates.
10.2
Platform Identification and CPUID
In addition to verifying the processor signature, the intended processor platform type
must be determined to properly target the microcode update. The intended processor
platform type is determined by reading bits [52:50] of the IA32_PLATFORM_ID
register, (MSR 17h) within the processor. This is a 64-bit register that must be read
using the RDMSR instruction. The 3 Platform Id bits, when read as a binary coded
decimal (BCD) number, indicate the bit position in the microcode update header’s
Processor Flags field that is asSoCiated with the installed processor.
must be determined to properly target the microcode update. The intended processor
platform type is determined by reading bits [52:50] of the IA32_PLATFORM_ID
register, (MSR 17h) within the processor. This is a 64-bit register that must be read
using the RDMSR instruction. The 3 Platform Id bits, when read as a binary coded
decimal (BCD) number, indicate the bit position in the microcode update header’s
Processor Flags field that is asSoCiated with the installed processor.
Executing the CPUID instruction with EAX=1 will provide the following information.
10.3
References
For further details of Intel
®
64 and IA-32 architectures, refer to Intel
®
64 and IA-32
Architectures Software Developer’s Manual Combined Volumes:1, 2A, 2B, 2C, 3A, 3B,
and 3C:
and 3C:
•
http://www.intel.com/content/www/µs/en/processors/architectures-software-
developer-manuals.html
developer-manuals.html
§
EAX
Field description
[31:28]
Reserved
[27:20]
Extended Family value
[19:16]
Extended Model value
[15:13]
Reserved
[12]
Processor Type Bit
[11:8]
Family value
[7:4]
Model value
[3:0]
Stepping ID Value