Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
PCU – System Management Bus (SMBus)
1126
Datasheet
22.8.1
Host Status Register (SMB_Mem_HSTS_io)—Offset 0h
All status bits are set by hardware and cleared by the software writing a one to the
particular bit position. Writing a zero to any bit position has no affect
Access Method
Default: 00h
Type: I/O Register
(Size: 8 bits)
SMB_Mem_HSTS_io: [IOBAR] + 0h
IOBAR Type: PCI Configuration Register (Size: 32 bits)
IOBAR Reference: [B:0, D:31, F:3] + 20h
IOBAR Reference: [B:0, D:31, F:3] + 20h
7
4
0
0
0
0
0
0
0
0
0
BDS
IUS
SMB
_
A
LE
R
T
B
FA
IL
E
D
BERR
DEV
E
RR
INTR
HB
SY
Bit
Range
Default &
Access
Description
7
0b
RW
BDS: BYTE_DONE_STS (BDS) - This bit will be set to 1 when the host controller has
received a byte (for Block Read commands) or if it has completed transmission of a byte
(for Block Write commands) when the 32-byte buffer is not being used. Note that this
bit will be set, even on the last byte of the transfer. Software clears the bit by writing a
1 to the bit position. This bit has no meaning for block transfers when the 32-byte buffer
is enabled.Note: When the last byte of a block message is received, the host
controller will set this bit. However, it will not immediately set the INTR bit (bit
1 in this register). When the interrupt handler clears the BYTE_DONE_STS bit,
the message is considered complete, and the host controller will then set the
INTR bit (and generate another interrupt). Thus, for a block message of n
bytes, the SMBus host will generate n+1 interrupts. The interrupt handler
needs to be implemented to handle these cases.
6
0b
RW
IUS: In Use Status (IUS) - After a full PCI reset, a read to this bit returns a 0. After the
first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next
read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it
reads a 0, and will then own the usage of the host controller. This bit has no other effect
on the hardware, and is only used as semaphore among various independent software
threads that may need to use the SMBus host
5
0b
RW
SMB_ALERTB: the processor sets this bit to a '1' to indicates source of the interrupt or
SMI# was the SMB_ALERTB signal. Software resets this bit by writing a 1 to this
location.
4
0b
RW
FAILED: Failed (FAIL) - When set, this indicates that the source of the interrupt or SMI
was a failed bus transaction. This is set in response to the KILL bit being set to
terminate the host transaction.
3
0b
RW
BERR: Bus Error (BERR) - When set, this indicates the source of the interrupt or SMI
was a transaction collision.
2
0b
RW
DEVERR: Device Error (DERR) - When set, this indicates that the source of the interrupt
or SMI was due one of the following: Illegal Command Field Unclaimed Cycle (host
initiated) Host Device Time-out Error. CRC Error Write Protection Access Error (START
bit will be cleared, Device Error will be set and Host Busy is never set because SMB
Transaction never took place).
1
0b
RW
INTR: Interrupt (INTR) - When set, this indicates that the source of the interrupt or SMI
was the successful completion of its last command.
0
0b
RW
HBSY: Host Busy (HBSY) - A '1' indicates that the SMBus host is running a command
from the host interface. No SMB registers should be accessed while this bit is set.
Exception: The BLOCK DATA REGISTER can be accessed when this bit is set ONLY when
the SMB_CMD bits (in Host control register) are programmed for Block command or I2C
Read command. This is necessary in order to check the DONE_STS bit.