Intel J1850 FH8065301455200 User Manual

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Datasheet

The system memory controller supports the following DDR3L, DRAM technologies, Data 
Transfer Rates, SO-DIMM Modules and other features:

•

DDR3L Data Transfer Rates (Fixed per SKU): 1066MT/s (8.5 GB/s per channel) or 
1333MT/s (10.6 GB/s per channel)

•

DDR3L SDRAM (1.35 V DRAM interface I/Os, including DDR3L)

•

DDR3L SO-DIMM Modules (unbuffered)
— Raw Card A = 2 rank of x16 SDRAM (double sided)
— Raw Card B = 1 rank of x8 SDRAM (double sided)

DRAM1_CKP[2,0]

DRAM1_CKN[2,0]

O

DDR3

SDRAM and inverted Differential Clock: (1 pair per Rank)
The differential clock pair is used to latch the command into DRAM. 

Each pair corresponds to one rank on DRAM side.

DRAM1_CS[2,0]#

O

DDR3

Chip Select: (1 per Rank). Used to qualify the command on the 

command bus for a particular rank.

DRAM1_CKE[2,0]

O

DDR3

Clock Enable: (power management)
It is used during DRAM power up/power down and Self refresh. 
Note: DDR3L uses only DRAM1_CKE[0,2]. DRAM1_CKE[1,3] are not 

being used for DDR3L.

DRAM1_MA[15:0]

O

DDR3

Memory Address: Memory address bus for writing data to memory 

and reading data from memory. These signals follow common clock 

protocol relative to DRAM1_CKN, DRAM1_CKP pairs

DRAM1_BS[2:0]

O

DDR3

Bank Select: These signals define which banks are selected within 

each DRAM rank

DRAM1_RAS#

O

DDR3

Row Address Select: Used with DRAM1_CAS# and DRAM1_WE# 

(along with DRAM1_CS#) to define the DRAM Commands

DRAM1_CAS#

O

DDR3

Column Address Select: Used with DRAM1_RAS# and DRAM1_WE# 

(along with DRAM1_CS#) to define the SRAM Commands

DRAM1_WE#

O

DDR3

Write Enable Control Signal: Used with DRAM1_WE# and 

DRAM1_CAS# (along with control signal, DRAM1_CS#) to define the 

DRAM Commands.

DRAM1_DQ[63:0]

I/O

DDR3

Data Lines: Data signal interface to the DRAM data bus.

DRAM1_DM[7:0]

O

DDR3

Data Mask: DM is an output mask signal for write data. Output data 

is masked when

 

DM is sampled HIGH coincident with that output data 

during a Write access. DM is sampled on both edges of DQS.

DRAM1_DQSP[7:0]

DRAM1_DQSN[7:0]

I/O

DDR3

Data Strobes: The data is captured at the crossing point of 

DRAM1_DQSP[7:0] and its compliment ‘N’ during read and write 

transactions.
For reads, the strobe crossover and data are edge aligned, whereas in 

the Write command, the strobe crossing is in the centre of the data 

window.

DRAM1_ODT[2,0]

O

DDR3

On Die Termination: ODT signal going to DRAM in order to turn ON 

the DRAM ODT during Write.

DRAM1_DRAMRST#

O

Reset DRAM: This signal can be used to reset DRAM devices.