Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
1181
PCU – iLB – Low Pin Count (LPC) Bridge
24.2
Features
The LPC interface to the processor is shown in
. Note that the processor
implements all of the signals that are shown as optional, but peripherals are not
required to do so.
required to do so.
Note:
The LPC controller does not implement bus mastering cycles or DMA.
NOTES:
1.
The General Purpose Input (GPI) must use a SMI capable GPIO: GPIO_S0_SC[7:0].
Table 170. LPC Signals
Signal Name
Direction/
Type
Description
ILB_LPC_AD[3:0]
I/O
CMOS3.3/1.8
LPC Multiplexed Command, Address, Data: Internal pull-ups are provided for
these signals.
These signals are multiplexed and may be used by other functions.
These signals are multiplexed and may be used by other functions.
ILB_LPC_CLK[0]
O
CMOS3.3/1.8
LPC Clock [0] Out: 25 MHz PCI-like clock driven to LPC peripherals.
These signals are multiplexed and may be used by other functions.
These signals are multiplexed and may be used by other functions.
ILB_LPC_CLK[1]
O or I
CMOS3.3/1.8
LPC Clock [1] Out: 25 MHz PCI-like clock driven to LPC peripherals. Can be
configured as an input to compensate for board routing delays through Soft Strap.
These signals are multiplexed and may be used by other functions.
These signals are multiplexed and may be used by other functions.
ILB_LPC_CLKRUN#
I/OD
CMOS3.3/1.8
LPC Clock Run: Input to determine the status of ILB_LPC_CLK and an open drain
output used to request starting or speeding up ILB_LPC_CLK. This is a sustained tri-
state signal used by the central resource to request permission to stop or slow
ILB_LPC_CLK. The central resource is responsible for maintaining the signal in the
asserted state when ILB_LPC_CLK is running and deasserts the signal to request
permission to stop or slow ILB_LPC_CLK. An internal pull-up is provided for this
signal.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
ILB_LPC_FRAME#
O
CMOS3.3/1.8
LPC Frame: This signal indicates the start of an LPC cycle, or an abort.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
ILB_LPC_SERIRQ
I/O
CMOS1.8
Serial Interrupt Request: This signal implements the serial interrupt protocol.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
Figure 27. LPC Interface Diagram
S O C
L P C D e v ic e
L C L K
L R E S E T #
S E R IR Q (O p tio n a l)
L A D [3 :0 ]
L F R A M E #
L P C P D # (O p tio n a l)
P M C _ S U S _ S T A T #
L S M I# (O p tio n a l)
G P I
1
C L K R U N # (O p tio n a l)
IL B _ L P C _ C L K R U N #
IL B _ L P C _ S E R IR Q
IL B _ L P C _ C L K
P M C _ P L T R S T #
IL B _ L P C _ F R A M E #
IL B _ L P C _ A D [3 :0 ]