Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
1187
PCU – iLB – Low Pin Count (LPC) Bridge
24.3.2
LPC Power Management
24.3.2.1
Clock Enabling
The LPC clocks can be enabled or disabled by setting or clearing, respectively, the
LPCC.LPCCLK[1:0]EN bits.
LPCC.LPCCLK[1:0]EN bits.
24.3.2.2
Clock Run Enable
The Clock Run protocol is disabled by default and should only be enabled during
operating system run-time, once all LPC devices have been initialized. The Clock Run
protocol is enabled by setting the LPCC.CLKRUN_EN register bit.
operating system run-time, once all LPC devices have been initialized. The Clock Run
protocol is enabled by setting the LPCC.CLKRUN_EN register bit.
24.3.3
SERIRQ Disable
Serialized IRQ support may be disabled by setting the OIC.SIRQEN bit to 0b.
24.4
References
•
Implementing Industry Standard Architecture (ISA) with Intel
24.5
Register Map
for additional information.