Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
1247
PCU – iLB – IO APIC
30
PCU – iLB – IO APIC
The IO Advanced Programmable Interrupt Controller (APIC) is used to support line
interrupts more flexibly than the 8259 PIC. Line interrupts are routed to it from
multiple sources, including legacy devices, using the interrupt decoder and serial IRQs,
or they are routed to it from the interrupt router in the iLB. These line based interrupts
are then used to generate interrupt messages targeting the local APIC in the processor.
interrupts more flexibly than the 8259 PIC. Line interrupts are routed to it from
multiple sources, including legacy devices, using the interrupt decoder and serial IRQs,
or they are routed to it from the interrupt router in the iLB. These line based interrupts
are then used to generate interrupt messages targeting the local APIC in the processor.
30.1
Features
•
87 interrupt lines
— IRQ0-86
•
Edge or level trigger mode per interrupt
•
Active low or high polarity per interrupt
•
Works with local APIC in processor via MSIs
•
MSIs can target specific processor core
•
Established APIC programming model
I
O
I
O
I
O
I
O
I
O
I
O
I
O
O
Platform Control Unit
UAR
T
LP
C
GPIO
RT
C
C
HP
ET
ET
82
59
59
APIC
82
54
54
SMB
iLB
SP
I
I
PMC