Intel J1850 FH8065301455200 User Manual

Product codes
FH8065301455200
Page of 1272
Datasheet
131
Graphics, Video, and Display
12.7
Features
The 3D graphics pipeline architecture simultaneously operates on different primitives or 
on different portions of the same primitive. All the cores are fully programmable, 
increasing the versatility of the 3D Engine. The Gen 7.0 3D engine provides the 
following performance and power-management enhancements:
Hierarchal-Z
Video quality enhancements
12.7.1
3D Engine Execution Units
The EUs perform 128-bit wide execution per clock.
Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel 
processing.
12.7.2
3D Pipeline
12.7.2.1
Vertex Fetch (VF) Stage
The VF stage executes 3DPRIMITIVE commands. Some enhancements have been 
included to better support legacy D3D APIs as well as SGI OpenGL*.
12.7.2.2
Vertex Shader (VS) Stage
The VS stage performs shading of vertices output by the VF function. The VS unit 
produces an output vertex reference for every input vertex reference received from the 
VF unit, in the order received.
Figure 16. 3D Graphics Block Diagram