Intel J1850 FH8065301455200 User Manual

Datasheet

135

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CMOS1.8

Serial ATA 0 General Purpose: This is an input pin that can be 

configured as an interlock switch or as a general purpose I/O, 

depending on the platform. When used as an interlock switch status 

indication, this signal should be driven to ‘0’ to indicate that the 

switch is closed, and to ‘1’ to indicate that the switch is open.

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CMOS1.8

Serial ATA 1 General Purpose: Same as above.

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CMOS1.8_OD

Serial ATA LED: This is an open-collector output pin driven during 

SATA command activity. It is to be connected to external circuitry 

that can provide the current to drive a platform LED. When active, 

the LED is on. When tri-stated, the LED is off.

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SATA

Serial ATA Port 1 and 0: These are outbound high-speed 

differential signals to Port 1 and 0.

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SATA

Serial ATA Port 1 and 0: These are inbound high-speed differential 

signals to Port 1 and 0.

I/O

SATA

These pins are used for hardware DEVSLP enabling.
SATA_DEVSLP[0] is multiplexed with SATA_GPI[1], MMC1_RST#.

SATA_RCOMP_P
SATA_RCOMP_N

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These pins are used to connect the external resistors used for 

Rcomp.

Native Command Queuing (NCQ)

Allows the device to reorder commands for more efficient data transfers

Auto Activate for DMA

Collapses a DMA Setup then DMA Activate sequence into a DMA Setup 

only

Hot Plug Support

Allows for device detection without power being applied and ability to 

connect and disconnect devices without prior notification to the system

Asynchronous Signal Recovery

Provides a recovery from a loss of signal or establishing communication 

after hot plug

3 Gb/s Transfer Rate

Capable of data transfers up to 3 Gb/s

ATAPI Asynchronous Notification

A mechanism for a device to send a notification to the host that the 

device requires attention

Host & Link Initiated Power 

Management

Capability for the host controller or device to request Partial and 

Slumber interface power states

Staggered Spin-Up

Enables the host to spin up hard drives sequentially to prevent power 

load problems on boot

Command Completion Coalescing

Reduces interrupt and completion overhead by allowing a specified 

number of commands to complete and then generating an interrupt to 

process the commands