Intel J1850 FH8065301455200 User Manual

Intel

Product codes

FH8065301455200

Datasheet

139

Serial ATA (SATA)

13.5

SATA PCI Configuration Registers

Table 100.

Summary of SATA PCI Configuration Registers—0/19/0

Offset

Size

Register ID—Description

Default

Value

0h

4

“Identifiers (ID)—Offset 0h” on page 140

0F208086h

4h

2

“Command (CMD)—Offset 4h” on page 141

0000h

6h

2

“Device Status (STS)—Offset 6h” on page 142

02B0h

8h

1

“Revision ID (RID)—Offset 8h” on page 143

00h

9h

1

“Programming Interface (PI)—Offset 9h” on page 143

8Ah

Ah

2

“Class Code (CC)—Offset Ah” on page 144

0106h

Ch

1

“Cache Line Size (CLS)—Offset Ch” on page 144

00h

Dh

1

“Master Latency Timer (MLT)—Offset Dh” on page 145

00h

Eh

1

“Header Type (HTYPE)—Offset Eh” on page 145

00h

10h

4

“Primary Command Block Base Address (PCMDBA)—Offset 10h” on page 146

00000001h

14h

4

“Primary Control Block Base Address (PCTLBA)—Offset 14h” on page 146

00000001h

18h

4

“Secondary Command Block Base Address (SCMDBA)—Offset 18h” on page 147

00000001h

1Ch

4

“Secondary Control Block Base Address (SCTLBA)—Offset 1Ch” on page 147

00000001h

20h

4

“Legacy IDE Base Address / AHCI Index Data Pair Base Address (LBAR)—Offset

20h” on page 148

00000001h

24h

4

“AHCI Base Address/Serial ATA Index Data Pair Base Address (ABAR)—Offset 24h”

00000000h

2Ch

4

“Sub System Identifiers (SS)—Offset 2Ch” on page 149

00000000h

34h

1

“Capabilities Pointer (CAP)—Offset 34h” on page 150

80h

3Ch

2

“Interrupt Information (INTR)—Offset 3Ch” on page 150

0100h

3Eh

1

“Minimum Grant (MGNT)—Offset 3Eh” on page 151

00h

3Fh

1

“Maximum Latency (MLAT)—Offset 3Fh” on page 151

00h

40h

2

“Primary Timing (PTIM)—Offset 40h” on page 152

0000h

42h

2

“Secondary Timing (STIM)—Offset 42h” on page 153

0000h

44h

1

“Device 1 IDE Timing (D1TIM)—Offset 44h” on page 154

00h

48h

1

“Synchronous DMA Control (Synchronous_DMA_Control)—Offset 48h” on page 154

00h

4Ah

2

“Synchronous_DMA_Timing—Offset 4Ah” on page 155

0000h

54h

4

“IDE I/O Configuration (IIOC)—Offset 54h” on page 155

00000000h

70h

2

“PCI Power Management Capability ID (PID)—Offset 70h” on page 156

A801h

72h

2

“Primary Command Block Base Address (PCMDBA)—Offset 10h” on page 146

4003h

74h

2

“PCI Power Management Control and Status (PMCS)—Offset 74h” on page 157

0008h

80h

2

“Message Signaled Interrupt Identifier (MID)—Offset 80h” on page 158

7005h

82h

2

“Message Signaled Interrupt Message Control (MC)—Offset 82h” on page 158

0000h

84h

4

“Message Signaled Interrupt Message Address (MA)—Offset 84h” on page 159

00000000h

88h

2

“Message Signaled Interrupt Message Data (MD)—Offset 88h” on page 159

0000h

90h

2

“Port Mapping Register (MAP)—Offset 90h” on page 160

0420h

92h

2

“Port Control and Status (PCS)—Offset 92h” on page 161

0000h