Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
169
Serial ATA (SATA)
13.5.46
BIST FIS Transmit Data 1 (BFTD1)—Offset E4h
Access Method
Default: 00000000h
13.5.47
BIST FIS Transmit Data 2 (BFTD2)—Offset E8h
Access Method
Default: 00000000h
Type: PCI Configuration Register
(Size: 32 bits)
BFTD1: [B:0, D:19, F:0] + E4h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DA
TA
Bit
Range
Default &
Access
Description
31:0
0h
RW
Data (DATA): The data programmed into this register will form the contents of the
second DW of any BIST FIS initiated by the SATA controller. This register is not port
specific - its contents will be used for BIST FIS initiated on any port. Although the 2nd
and 3rd DWs of the BIST FIS are only meaningful when the T bit of the BIST FIS is set to
indicate Far-End Transmit mode, this register's contents will be transmitted as the BIST
FIS 2nd DW regardless of whether or not the T bit is indicated in the BFCS register.
Type: PCI Configuration Register
(Size: 32 bits)
BFTD2: [B:0, D:19, F:0] + E8h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DA
TA
Bit
Range
Default &
Access
Description
31:0
0h
RW
Data (DATA): The data programmed into this register will form the contents of the
third DW of any BIST FIS initiated by the SATA controller. This register is not port
specific - its contents will be used for BIST FIS initiated on any port. Although the 2nd
and 3rd DWs of the BIST FIS are only meaningful when the T bit of the BIST FIS is set to
indicate Far-End Transmit mode, this register's contents will be transmitted as the BIST
FIS 3rd DW regardless of whether or not the T bit is set in the BFCS register.