Intel J1850 FH8065301455200 User Manual

20

Datasheet

•

No wake on audio (modem) support

The Intel TXE

system contains a security engine and additional hardware security 

features that enable a secure and robust platform. 

See 

 for more details.

Security features include:

•

Isolated execution environment for crypto operations (SKU-enabled)

•

Supports secure boot – with customer programmable keys to secure code

The SoC requires TXE firmware in the PCU SPI flash image to function.

The platform controller unit is a collection of HW blocks, including SMBus, UART, 
debug/boot SPI, and Intel legacy block (iLB), that are critical to implement a Windows* 
compatible platform. See 

 for 

links to more information about each interface.

Key PCU features include:

•

SMBus Host controller – supports SMBus 2.0 specification

•

Universal Asynchronous Receiver/Transmitter (UART) with COM1 interface

•

A Serial Peripheral Interface (SPI) for Flash only – stores boot FW and system 
configuration data

•

Intel Legacy Block (iLB) supports legacy PC platform features

— RTC, Interrupts, Timers, General Purpose I/Os (GPIO), and Peripheral interface 

(LPC for TPM) blocks.

This processor is packaged in a Flip-Chip Ball Grid Array (FCBGA) package with 1170 
solder balls with 0.593 mm (minimum) ball pitch. The package dimensions are 25 mm 
x 27 mm. See 

 for more details.

The processor SKUs are listed in the following table.