Intel J1850 FH8065301455200 User Manual

Datasheet

45

ECAM accesses are only possible when BUNIT.BECREG.ECENABLE (bit 0) is set.

Pseudo code for an enhanced PCI configuration register read is shown below:

•

MyCfgAddr[27:20] = bus; MyCfgAddr[19:15] = device; MyCfgAddr[14:12] = 
funct;

•

MyCfgAddr[11:2] = dw_offset; MyCfgAddr[31:28] = BECREG[31:28];

•

Register_Snapshot = MEMREAD(MyCfgAddr)

Accesses to the message bus space is through the Processor Transaction Router’s PCI 
configuration registers. This unit relies on three 32-bit PCI configuration registers to 
generate messages:

•

Message Bus Control Register (MCR) – PCI[B:0,D:0,F:0] + D0h

•

Message Data Register (MDR) – PCI[B:0,D:0,F:0] + D4h

•

Message Control Register eXtension (MCRX) – PCI[B:0,D:0,F:0] + D8h

This indirect access mode is similar to PCI CAM. Software uses the MCR/MCRX as an 
index register, indicating which message bus space register to access (MCRX only when 
required), and MDR as the data register. Writes to the MCR trigger message bus 
transactions.

Writes to MCRX and MDR will be captured. Writes to MCR will generate an internal 
‘message bus’ transaction with the opcode and target (port, offset, bytes) specified in 
the MCR and the captured MCRX. When a write opcode is specified in the MCR, the data 
that was captured by MDR is used for the write. When a data read opcode is specified in 
the MCR, the data will be available in the MDR register after the MCR write completes 
(non-posted). The format of MCR and MCRX are shown in the following tables.

Use from BAR: BUNIT.BECREG[31:28]

31:28

Bus Number

27:20

Device Number

19:15

Function Number

14:12

Register Number

11:02