Intel J1850 FH8065301455200 User Manual

Product codes
FH8065301455200
Page of 1272
Power Management
64
Datasheet
6.2.7
Interface State Combinations
6.3
Processor Core Power Management
While executing code, Enhanced Intel
®
 SpeedStep
®
 Technology optimizes the 
processor’s frequency and core voltage based on workload. Each frequency and voltage 
operating point is defined by ACPI as a P-state. When the processor is not executing 
code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower 
power C-states have longer entry and exit latencies.
6.3.1
Enhanced Intel
®
 SpeedStep
®
 Technology
The following are the key features of Enhanced Intel
®
 SpeedStep
®
 Technology:
Applicable to processor Core Voltage and Graphic Core Voltage
Multiple frequency and voltage points for optimal performance and power 
efficiency. These operating points are known as P-states.
Table 47. G, S and C State Combinations
Global (G) 
State
Sleep 
(S) State
Processor 
Core
(C) State
Processor 
State 
System Clocks
Description
G0
S0
C0 
Full On
On 
Full On
G0
S0
C1
Auto-Halt
On
Auto-Halt
G0
S0
C6
Deep Power 
Down
On
Deep Power Down
G1
S3
Power off
Off except RTC & 
internal ring OSC
Suspend to RAM
G1
S4
Power off
Off except RTC & 
internal ring OSC
Suspend to Disk
G2
S5
Power off
Off except RTC & 
internal ring OSC
Soft Off
G3
NA
Power Off
Power off
Hard Off
Table 48. D, S and C State Combinations
Graphics Adapter 
(D) State
Sleep (S) State
 (C) State
Description
D0
S0
C0
Full On, Displaying
D0
S0
C1
Auto-Halt, Displaying
D0
S0
C6
Deep Sleep, Display Off
D3
S0
Any
Not Displaying
D3
S3
Not Displaying
Graphics Core power off.
D3
S4
Not Displaying
Suspend to disk
Core power off