Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
849
PCI Express* 2.0
17.11
PCI Express* Lane 2 Electrical Address Map
Table 132.
Summary of PCI Express* Lane 2 Electrical Message Bus Registers—0xA6
(Global Offset 600h)
Offset
Register ID—Description
Default
Value
0h
00010080h
4h
00600060h
8h
00000000h
Ch
5515ACAAh
10h
575555C1h
14h
00003E63h
18h
FFFFFFFFh
1Ch
00000009h
20h
000000C4h
24h
00000000h
28h
00000000h
2Ch
0F000000h
30h
00250F00h
34h
00000000h
38h
007A0018h
3Ch
04100300h
40h
01000001h
44h
01000001h
48h
00008080h
4Ch
00004F10h
50h
80808080h
54h
80808080h
58h
00000000h
5Ch
00180888h
60h
0001C020h