Intel J1850 FH8065301455200 User Manual

92

Datasheet

1.

For embedded connection, support of programmable voltage swing levels is optional.

2.

Total drive current of the transmitter when it is shorted to its ground.

3.

Common mode voltage is equal to Vbias_Tx voltage shown in 

4.

Straight loss line between 0.675 GHz and 1.35 GHz.

5.

All DisplayPort Main Link lanes as well as AUX CH must be AC coupled. AC coupling capacitors must be 

placed on the transmitter side. Placement of AC coupling capacitors on the receiver side is optional.

6.

AVcc =Analog Voltage level

V

TX-DIFFp-p-Level0

Differential Peak-to-peak
Output Voltage Level 0

0.34

0.4

0.46

V

1

V

TX-DIFFp-p-Level1

Differential Peak-to-peak
Output Voltage Level 1

0.51

0.6

0.68

V

1

V

TX-DIFFp-p-Level2

Differential Peak-to-peak
Output Voltage Level 2

0.69

0.8

0.92

V

1

VT

X-DIFFp-p-Level3

Differential Peak-to-peak
Output Voltage Level 3

0.85

1.2

1.38

V

1

V

TX-PREEMP-RATIO

No Pre-emphasis

0.0

0.0

0.0

dB

1

3.5 dB Pre-emphasis

2.8

3.5

4.2

dB

1

6.0 dB Pre-emphasis

4.8

6.0

7.2

dB

1

9.5 dB Pre-emphasis

7.5

9.5

11.4

dB

1

V

TX-DC-CM

Tx DC Common Mode
Voltage

0

2.0

V

1

RLTX-DIFF

Differential Return Loss at 

0.675GHz at Tx Package pins

12

dB

4

Differential Return Loss at 

1.35 GHz at Tx Package pins

9

dB

4

C

TX

AC Coupling Capacitor 

75

200

nF

5

Voff

Single Ended Standby (off), 

output voltage

-10

10

mV

6 @ AVcc

Vswing

Single Ended output swing 

voltage

400

600

mV

V

OH

 (<=165 MHz)

Single Ended high level, output 

voltage

-10

10

mv

6 @ AVcc

V

OH

(>165 MHz)

Single Ended high level, output 

voltage

-200

10

mV

6 @ AVcc

V

OL

(<=165 MHz)

Single Ended low level, output 

voltage

-600

-400

mV

6 @ AVcc

V

OL

(>165MHz)

Single Ended low level, output 

voltage

-700

-400

mV

6 @ AVcc