Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Platform Controller Unit (PCU) Overview
946
Datasheet
•
Power Management Controller (PMC)
— Controls many of the power management features present in the processor.
— Controls many of the power management features present in the processor.
•
Intel Legacy Block (iLB)
— Supports legacy PC platform features
— Sub-blocks include LPC, GPIO, 8259 PIC, IO-APIC, 8254 timers, HPET timers
— Supports legacy PC platform features
— Sub-blocks include LPC, GPIO, 8259 PIC, IO-APIC, 8254 timers, HPET timers
and the RTC.
18.1.1
BIOS/EFI Top Swap
While updating the BIOS/EFI boot sector in flash, unexpected system power loss can
cause an incomplete write resulting in a corrupt boot sector. For this reason, two boot
sectors are stored in the flash.
cause an incomplete write resulting in a corrupt boot sector. For this reason, two boot
sectors are stored in the flash.
The location of the secondary boot sector is defined by inverting one of the bits of the
address (A16, A17 or A18) that the CPU core will attempt to fetch code from. This
address bit will vary depending on the size of the boot block. Refer to the GCS.BBSize
register bit definition for further details.
address (A16, A17 or A18) that the CPU core will attempt to fetch code from. This
address bit will vary depending on the size of the boot block. Refer to the GCS.BBSize
register bit definition for further details.
Prior to starting writes to the primary BIOS/EFI boot sector, the Top-Swap indicator is
set. From this point onwards, the secondary boot sector will be used. Only after
successful completion of the primary boot sector write should the Top-Swap indicator
be cleared and the primary boot sector be used again.
set. From this point onwards, the secondary boot sector will be used. Only after
successful completion of the primary boot sector write should the Top-Swap indicator
be cleared and the primary boot sector be used again.
There are two methods that can be used to implement the Top-Swap indicator.
18.1.1.1
BIOS/EFI Controlled
BIOS/EFI can use the GCS.TS register bit to set the Top-Swap indicator. The GCS.TS bit
is stored in the RTC well and, therefore, keeps its value even when the system is
powered down.
is stored in the RTC well and, therefore, keeps its value even when the system is
powered down.
Note:
Writes to GCS.TS will be unsuccessful if the GCS.BILD bit has been set.
18.1.1.2
Hardware Controlled
System hardware, external to the processor, can be used to assert or de-assert the
Top-Swap strapping input signal. If the signal is sampled as being asserted during
power-up then Top-Swap is active.
Top-Swap strapping input signal. If the signal is sampled as being asserted during
power-up then Top-Swap is active.
Note:
The Top-Swap strap is an active high signal and is multiplexed with the
GPIO_S0_SC[56] signal.
GPIO_S0_SC[56] signal.
Note:
The Top-Swap strap, when asserted at power-up, forces Top-Swap to be active even if
GCS.TS bit is cleared but doesn't change the GCS.TS bit itself. The GCS.TS bit can not
be changed if Top-Swap pin strap was sampled as being asserted until the next power-
up when Top-Swap is sampled as being de-asserted.
GCS.TS bit is cleared but doesn't change the GCS.TS bit itself. The GCS.TS bit can not
be changed if Top-Swap pin strap was sampled as being asserted until the next power-
up when Top-Swap is sampled as being de-asserted.