Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
959
PCU – Power Management Controller (PMC)
19.2
Features
19.2.1
Sx-G3-Sx, Handling Power Failures
Depending on when the power failure occurs and how the system is designed, different
transitions could occur due to a power failure.
transitions could occur due to a power failure.
The GEN_PMCON1.AG3E bit provides the ability to program whether or not the system
should boot once power returns after a power loss event. If the policy is to not boot,
the system remains in an S5 state (unless previously in S4). There are only two
possible events that will wake the system after a power failure.
should boot once power returns after a power loss event. If the policy is to not boot,
the system remains in an S5 state (unless previously in S4). There are only two
possible events that will wake the system after a power failure.
•
PMC_PWRBTN#: PMC_PWRBTN# is always enabled as a wake event. When
RSMRST# is low (G3 state), the PM1_STS_EN.PWRBTN_STS bit is reset. When the
processor exits G3 after power returns (PMC_RSMRST# goes high), the
PMC_PWRBTN# signal is already high (because the suspend plane goes high before
PMC_RSMRST# goes high) and the PM1_STS_EN.PWRBTN_STS bit is 0b.
RSMRST# is low (G3 state), the PM1_STS_EN.PWRBTN_STS bit is reset. When the
processor exits G3 after power returns (PMC_RSMRST# goes high), the
PMC_PWRBTN# signal is already high (because the suspend plane goes high before
PMC_RSMRST# goes high) and the PM1_STS_EN.PWRBTN_STS bit is 0b.
•
RTC Alarm: The PM1_STS_EN.RTC_EN bit is in the RTC well and is preserved after
a power loss. Like PM1_STS_EN.PWRBTN_STS the PM1_STS_EN.RTC_STS bit is
cleared when PMC_RSMRST# goes low.
a power loss. Like PM1_STS_EN.PWRBTN_STS the PM1_STS_EN.RTC_STS bit is
cleared when PMC_RSMRST# goes low.
The processor monitors both PMC_CORE_PWROK and PMC_RSMRST# to detect for
power failures. If PMC_CORE_PWROK goes low, the GEN_PMCON1.PWR_FLR bit is set.
If PMC_RSMRST# goes low, GEN_PMCON1.SUS_PWR_FLR is set.
power failures. If PMC_CORE_PWROK goes low, the GEN_PMCON1.PWR_FLR bit is set.
If PMC_RSMRST# goes low, GEN_PMCON1.SUS_PWR_FLR is set.
PMC_WAKE_PCIE[2]#
I
CMOS
PCI Express* Port 2 Wake Event: Sideband wake signal on
PCI Express asserted by a component requesting wake up.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
PMC_WAKE_PCIE[3]#
I
CMOS
PCI Express* Port 3 Wake Event: Sideband wake signal on
PCI Express asserted by a component requesting wake up.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
PMC_PLT_CLK[5:0]
O
CMOS
Platform Clocks: Configurable single ended clocks,
configurable to 19.2 MHz or 25 MHz.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
Table 138. PMC Signals (Sheet 3 of 3)
Signal Name
Direction/
Type
Description
Table 139. Transitions Due to Power Failure
State at Power Failure
GEN_PMCON1.AG3E bit
Transition When Power Returns
S0, S3
1
0
S5
S0
S4
1
0
S4
S0
S5
1
0
S5
S0