Intel Pentium D 830 HH80551PG0802MN Data Sheet

28

The signals A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize CMOS input buffers. GTL+ 
asynchronous signals follow the same DC requirements as GTL+ signals; however, the outputs are 
not actively driven high (during a logical 0 to 1 transition) by the processor. GTL+ asynchronous 
signals do not have setup or hold time specifications in relation to BCLK[1:0]. 

All of the GTL+ Asynchronous signals are required to be asserted/deasserted for at least six 
BCLKs in order for the processor to recognize the proper signal state. See 

specifications for the GTL+ Asynchronous signal groups. See 

 for additional timing 

requirements for entering and leaving the low power states.

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, 
BNR#, BOOTSELECT

1

, BPRI#, D[63:0]#, 

DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, 
DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#, 
HITM#, IMPSEL

, LOCK#, MCERR#, 

PROCHOT#, REQ[4:0]#, RS[2:0]#, RSP#, 
TRDY#, MSID[1:0]

1.

These signals have a 250–5000 

Ω pullup to V

TT

 rather than on-die termination.

A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[2:0], 
COMP[3:0], FERR#/PBE#, IERR#, IGNNE#, INIT#, 
LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#, 
SKTOCC#, SMI#, STPCLK#, TDO, TESTHI[13:0], 
THERMDA, THERMDC, THERMTRIP#, VID[5:0], 
VTTPWRGD, GTLREF[1:0], TCK, TDI, TRST#, TMS

2.

Signals that do not have R

TT

, nor are actively driven to their high-voltage level.

BSEL[2:0], VID[5:0], THERMTRIP#, FERR#/
PBE#, IERR#, BPM[5:0]#, BR0#, TDO, VTT_SEL, 
LL_ID[1:0]

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, 
BINIT#, BNR#, HIT#, HITM#, MCERR#, PROCHOT#, 
BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, 
BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, 
DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, 
LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

BOOTSELECT, VTTPWRGD, A20M#, IGNNE#, 
INIT#, PWRGOOD

1

, SMI#, STPCLK#, TCK

, TDI

, 

TMS

, TRST#

, MSID[1:0]

1.

These signals also have hysteresis added to the reference voltage. See 

 for more information.