Intel Pentium D 830 HH80551PG0802MN Data Sheet
Product codes
HH80551PG0802MN
Datasheet
29
Electrical Specifications
2.6.3
FSB DC Specifications
The processor front side bus DC specifications in this section are defined at the processor core
(pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless
otherwise stated.
(pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless
otherwise stated.
Table 2-10. BSEL[2:0] and VID[5:0] Signal Group DC Specifications
Symbol
Parameter
Max
Unit
Notes
1
,
2
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
These parameters are not tested and are based on design simulations.
R
ON
(BSEL)
Buffer On Resistance
60
Ω
-
R
ON
(VID)
Buffer On Resistance
60
Ω
-
I
OL
Max Land Current
8
mA
-
I
LO
Output Leakage Current
200
µA
3
3.
Leakage to V
SS
with land held at 2.5V.
V
TOL
Voltage Tolerance
V
TT
(max)
V
-
Table 2-11. GTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
1
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
IL
Input Low Voltage
0.0
GTLREF – (0.10 * V
TT
)
V
2, 3
2.
V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3.
The V
TT
referred to in these specifications is the instantaneous V
TT
.
V
IH
Input High Voltage
GTLREF + (0.10 * V
TT
)
V
TT
V
, 4, 5
4.
V
IH
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5.
V
IH
and V
OH
may experience excursions above V
TT
.
V
OH
Output High Voltage
N/A
V
TT
V
I
OL
Output Low Current
N/A
V
TT
/[(0.50*R
TT_MIN
) +
R
ON_MIN
]
A
-
I
LI
Input Leakage Current
N/A
± 200
µA
6
6.
Leakage to V
SS
with land held at V
TT
.
I
LO
Output Leakage
Current
Current
N/A
± 200
µA
R
ON
Buffer On Resistance
8
12
Ω