Intel Celeron 360 HH80552RE099512 User Manual

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The front side bus signals have been combined into groups by buffer type. GTL+ input 

signals have differential input buffers that use GTLREF[1:0] as a reference level. In this 

document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ 

I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as 

well as the GTL+ I/O group when driving. 

With the implementation of a source synchronous data bus comes the need to specify 

two sets of timing parameters. One set is for common clock signals that are dependent 

upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the 

source synchronous signals that are relative to their respective strobe lines (data and 

address) as well as the rising edge of BCLK0. Asychronous signals are still present 

(A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. 

 identifies which signals are common clock, source synchronous, and 

asynchronous.

GTL+ Common 
Clock Input

Synchronous to 
BCLK[1:0]

BPRI#, DEFER#, RS[2:0]#, RSP#, TRDY#

GTL+ Common 
Clock I/O

Synchronous to 
BCLK[1:0]

AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, 
DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, 
MCERR# 

GTL+ Source 
Synchronous I/O

Synchronous to 
assoc. strobe

GTL+ Strobes

Synchronous to 
BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

GTL+ 
Asynchronous 
Input

A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, 
STPCLK#, PWRGOOD, RESET#

GTL+ 
Asynchronous 
Output

FERR#/PBE#, IERR#, THERMTRIP#

GTL+ 
Asynchronous 
Input/Output

PROCHOT#

TAP Input

Synchronous to 
TCK

TCK, TDI, TMS, TRST#

REQ[4:0]#, A[16:3]#

2

ADSTB0#

A[35:17]#

2

ADSTB1#

D[15:0]#, DBI0# 

DSTBP0#, DSTBN0#

D[31:16]#, DBI1# 

DSTBP1#, DSTBN1#

D[47:32]#, DBI2# 

DSTBP2#, DSTBN2#

D[63:48]#, DBI3# 

DSTBP3#, DSTBN3#