Intel Celeron 360 HH80552RE099512 User Manual

25

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS 

input buffers. All of these signals follow the same DC requirements as GTL+ signals; 

however, the outputs are not actively driven high (during a logical 0 to 1 transition) by 

the processor. These signals do not have setup or hold time specifications in relation to 

BCLK[1:0]. 

All of the GTL+ Asynchronous signals are required to be asserted/de-asserted for at 

least six BCLKs in order for the processor to recognize the proper signal state. See 

 for the DC specifications for the GTL+ Asynchronous signal groups. See 

 for additional timing requirements for entering and leaving the low power 

states.

The processor DC specifications in this section are defined at the processor core (pads) 

unless otherwise stated. All specifications apply to all frequencies and cache sizes 

unless otherwise stated. 

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

V

IL

Input Low Voltage

0.0

GTLREF – (0.10 * V

TT

)

V

2, 3

2. V

IL

 is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. The V

TT

 referred to in these specifications is the instantaneous V

TT

.

V

IH

Input High Voltage

GTLREF + (0.10 * V

TT

)

V

TT

V

4, 5, 

3

4. V

IH

 is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5. V

IH

 and V

OH

 may experience excursions above V

TT

. However, input signal drivers must comply with the

signal quality specifications.

V

OH

Output High Voltage

0.90*V

TT

V

TT

V

3

, 

5

I

OL

Output Low Current

N/A

V

TT_MAX

/

[(0.50*R

TT_MIN

)+(R

ON_MIN

)]

A

-

I

LI

Input Leakage 
Current

N/A

± 200

µA

6

6. Leakage to V

SS

 with land held at V

TT

.

I

LO

Output Leakage 
Current

N/A

± 200

µA

7

7. Leakage to V

TT

 with land held at 300 mV.

R

ON

Buffer On Resistance

6

12

Ω