Intel Phi 7120A SC7120A Data Sheet
Product codes
SC7120A
Document ID Number: 328209 003EN
Intel
®
Xeon Phi™ Coprocessor Datasheet
65
The sensors available from the SMC vary within the Intel
®
Xeon Phi™ coprocessor
family of products. However, the IPMI SDR sensor names will not change from release
to release.
to release.
T
inlet
and T
outlet
are derived numbers based on the Inlet and Outlet temperature
sensors.
The sensors located on the Intel
®
Xeon Phi™ coprocessor relate information about the
CPU temperature as well as the temperature from three locations on the Intel
®
Xeon
Phi™ coprocessor. Currently, one sensor is located between memory chips near the PCI
Express* slot while the other two are located on the east and west sides of the card.
These are sometimes referred to as the “inlet” and “outlet” air temperature sensors but
they do not actually indicate airflow temperature but rather the temperature of the
board. The sensors are attached to the 12 inputs from the PCI Express* slot, the 2x3
connector, and the 2x4 connector. Input power can be estimated by summing the
currents over these three connections. For an actively cooled card, the SMC can also
provide the fan percentage PWM being used. Fan speed is a simple PID control with
setpoints set rather high to keep the sound level low when max cooling is not needed.
Express* slot while the other two are located on the east and west sides of the card.
These are sometimes referred to as the “inlet” and “outlet” air temperature sensors but
they do not actually indicate airflow temperature but rather the temperature of the
board. The sensors are attached to the 12 inputs from the PCI Express* slot, the 2x3
connector, and the 2x4 connector. Input power can be estimated by summing the
currents over these three connections. For an actively cooled card, the SMC can also
provide the fan percentage PWM being used. Fan speed is a simple PID control with
setpoints set rather high to keep the sound level low when max cooling is not needed.
6.5
System and Power Management
The Intel
®
Xeon Phi™ coprocessor PCI card supports both on-card power management
and an option for system-based management. With on-card power management, the
SMC adjusts system power using preprogrammed power throttle threshold values. With
system-based management, the SMC receives power control inputs via in-band
communication from a host application or out-of-band via IPMB commands from a host
BMC.
SMC adjusts system power using preprogrammed power throttle threshold values. With
system-based management, the SMC receives power control inputs via in-band
communication from a host application or out-of-band via IPMB commands from a host
BMC.
The Intel® Xeon Phi™ coprocessor supports 2 power threshold levels, PL0 and PL1,
which determine coprocessor power throttling points. These are not to be confused
with setting coprocessor power limits, that is, they do not change the absolute TDP of
the product.
which determine coprocessor power throttling points. These are not to be confused
with setting coprocessor power limits, that is, they do not change the absolute TDP of
the product.
PL1 is defined as the first power threshold. When the coprocessor detects that the
power consumption stays above PL1 for a specified time period, the coprocessor will
begin power throttling. By default, the card's PL1 power threshold is set to 105% of the
TDP, and the time duration allowed before throttling starts is 300 ms. When the SMC
detects that these conditions have been met it will assert power throttling, causing the
frequency to drop by about 100 MHz. Throttling will stop once the power consumption
drops 15 W or 20 W (depending on card TDP) below PL1. The difference in the
throttling assertion and deassertion thresholds will help prevent the coprocessor from
continually cycling between throttling and running normally. For cards with a TDP of
250 W or less, the deassertion point is 15 W lower than PL1. For 300 W cards the
deassertion point is 20 W below PL1.
power consumption stays above PL1 for a specified time period, the coprocessor will
begin power throttling. By default, the card's PL1 power threshold is set to 105% of the
TDP, and the time duration allowed before throttling starts is 300 ms. When the SMC
detects that these conditions have been met it will assert power throttling, causing the
frequency to drop by about 100 MHz. Throttling will stop once the power consumption
drops 15 W or 20 W (depending on card TDP) below PL1. The difference in the
throttling assertion and deassertion thresholds will help prevent the coprocessor from
continually cycling between throttling and running normally. For cards with a TDP of
250 W or less, the deassertion point is 15 W lower than PL1. For 300 W cards the
deassertion point is 20 W below PL1.
PL0 is normally set to a higher power threshold than PL1. By default, it is set to 125%
of TDP, and the time duration allowed at this power level is 50 ms. If these conditions
are met, the SMC will use the thermal throttling mechanism to force the coprocessor to
the lowest operating frequency which is around 600 MHz. The power reduction from
PL0 is expected to be much greater than PL1. The thermal throttling state will continue
until the total coprocessor power has dropped 40 W below PL0. When PL0 is exceeded,
the initial change in power consumption is a result of the lower operating frequency.
The coprocessor will also reduce the CPU core voltage to a value that is appropriate for
the lower frequency and this will provide additional power savings. The voltage
reduction takes place 3-400 msec after PL0 throttling is asserted.
of TDP, and the time duration allowed at this power level is 50 ms. If these conditions
are met, the SMC will use the thermal throttling mechanism to force the coprocessor to
the lowest operating frequency which is around 600 MHz. The power reduction from
PL0 is expected to be much greater than PL1. The thermal throttling state will continue
until the total coprocessor power has dropped 40 W below PL0. When PL0 is exceeded,
the initial change in power consumption is a result of the lower operating frequency.
The coprocessor will also reduce the CPU core voltage to a value that is appropriate for
the lower frequency and this will provide additional power savings. The voltage
reduction takes place 3-400 msec after PL0 throttling is asserted.