Intel Phi 7120A SC7120A Data Sheet

Intel

®

 Xeon Phi™ Coprocessor Datasheet

Document ID Number: 328209 003EN

64

Manageability, through the SMC, is achievable via the SCIF interface which is part of 
the MPSS software stack. This allows host programs to obtain MIC telemetry and other 
information from the SMC managed features of the Intel

®

 Xeon Phi™ coprocessor itself, 

as well as control SMC enabled functions. The SMC supports a host based SCIF 
interface.

The following SMC information and sensors are accessible over the host-based user 
mode SCIF interface:

• Hardware strapping pins
• SMC firmware revision number
• UUID
• PCI compliant Memory Mapped Input/Output (MMIO)
• Fan  tachometer
• Fan Pulse-Width-Modulation (PWM) to boost fan speed for additional cooling
• SMC System Event Log (SEL)
• All registers mentioned in the Ganglia support section
• Voltage rail discrete monitoring
• All discrete temperature sensors
• T

critical

• T

control

• T

current

• T

control offset adder

• Thermal throttle duration due to card power throttle threshold (in ms), free running 

counter that overflows at 60 seconds

• T

inlet

 (derived numbers)

• T

outlet

 (derived numbers)

• PERF_Status_Thermal
• 32-bit POST register
• SMC SEL Entry select and data registers (read only)
• SMC SDR Entry select and data registers (read only - required to interpret the SEL)

Each SMC sensor that is exposed over SCIF indicates one of four states in a consistent 
manner, returned in the same register value as the sensor reading itself, regardless of 
sensor type. These states do not apply to non-sensor information:

• Normal
• Upper critical
• Lower critical
• Inaccessible (sensor not available)

This minimizes the complexity of host-driven software and SMC firmware 
implementations.