Intel i3-4360T CM8064601481958 User Manual

•

Reduced possible overshoot/undershoot signal quality issues seen by the

processor I/O buffer receivers caused by reflections from potentially un-

terminated transmission lines.

When a given rank is not populated, the corresponding chip select and CKE signals are

not driven.

At reset, all rows must be assumed to be populated, until it can be determined that

the rows are not populated. This is due to the fact that when CKE is tri-stated with an

SO-DIMM present, the SO-DIMM is not ensured to maintain data integrity.

CKE tristate should be enabled by BIOS where appropriate, since at reset all rows

must be assumed to be populated.

The processor implements extensive support for power management on the SDRAM

interface. There are four SDRAM operations associated with the Clock Enable (CKE)

signals, which the SDRAM controller supports. The processor drives four CKE pins to

perform these operations.

The CKE is one of the power-save means. When CKE is off, the internal DDR clock is

disabled and the DDR power is reduced. The power-saving differs according to the

selected mode and the DDR type used. For more information, refer to the IDD table in

the DDR specification.

The processor supports three different types of power-down modes in package C0.

The different power-down modes can be enabled through configuring

"PM_PDWN_config_0_0_0_MCHBAR". The type of CKE power-down can be configured

through PDWN_mode (bits 15:12) and the idle timer can be configured through

PDWN_idle_counter (bits 11:0). The different power-down modes supported are:
•

No power-down (CKE disable)

•

Active power-down (APD): This mode is entered if there are open pages when

de-asserting CKE. In this mode the open pages are retained. Power-saving in this

mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this

mode is defined by tXP – small number of cycles. For this mode, DRAM DLL must

be on.

•

PPD/DLL-off: In this mode the data-in DLLs on DDR are off. Power-saving in this

mode is the best among all power modes. Power consumption is defined by

IDD2P1. Exiting this mode is defined by tXP, but also tXPDLL (10–20 according to

DDR type) cycles until first data transfer is allowed. For this mode, DRAM DLL

must be off.

The CKE is determined per rank, whenever it is inactive. Each rank has an idle-

counter. The idle-counter starts counting as soon as the rank has no accesses, and if

it expires, the rank may enter power-down while no new transactions to the rank

arrives to queues. The idle-counter begins counting at the last incoming transaction

arrival.

It is important to understand that since the power-down decision is per rank, the IMC

can find many opportunities to power down ranks, even while running memory

intensive applications; the savings are significant (may be few Watts, according to the

DDR specification). This is significant when each channel is populated with more

ranks.

Desktop 4th Generation Intel

®

 Core

™

 Processor Family, Desktop Intel

®

 Pentium

®

 Processor Family, and Desktop Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 328897-009

61