Intel i3-4360T CM8064601481958 User Manual

Selection of power modes should be according to power-performance or thermal

trade-offs of a given system:
•

When trying to achieve maximum performance and power or thermal

consideration is not an issue – use no power-down

•

In a system which tries to minimize power-consumption, try using the deepest

power-down mode possible – PPD/DLL-off with a low idle timer value

•

In high-performance systems with dense packaging (that is, tricky thermal

design) the power-down mode should be considered in order to reduce the heating

and avoid DDR throttling caused by the heating.

The default value that BIOS configures in "PM_PDWN_config_0_0_0_MCHBAR" is

6080h – that is, PPD/DLL-off mode with idle timer of 80h, or 128 DCLKs. This is a

balanced setting with deep power-down mode and moderate idle timer value.

The idle timer expiration count defines the # of DCKLs that a rank is idle that causes

entry to the selected powermode. As this timer is set to a shorter time, the IMC will

have more opportunities to put DDR in power-down. There is no BIOS hook to set this

register. Customers choosing to change the value of this register can do it by

changing it in the BIOS. For experiments, this register can be modified in real time if

BIOS does not lock the IMC registers.

During power-up, CKE is the only input to the SDRAM that has its level recognized

(other than the DDR3/DDR3L reset pin) once power is applied. It must be driven LOW

by the DDR controller to make sure the SDRAM components float DQ and DQS during

power-up. CKE signals remain LOW (while any reset is active) until the BIOS writes to

a configuration register. Using this method, CKE is ensured to remain inactive for

much longer than the specified 200 micro-seconds after power and clocks to SDRAM

devices are stable.

During S0 idle state, system memory may be conditionally placed into self-refresh

 for more details on conditional self-

refresh with Intel HD Graphics enabled.

When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh,

the processor core flushes pending cycles and then enters SDRAM ranks that are not

used by Intel graphics memory into self-refresh. The CKE signals remain LOW so the

SDRAM devices perform self-refresh.

The target behavior is to enter self-refresh for package C3 or deeper power states as

long as there are no memory requests to service.

Dynamic power-down of memory is employed during normal operation. Based on idle

conditions, a given memory rank may be powered down. The IMC implements

aggressive CKE control to dynamically put the DRAM devices in a power-down state.

The processor core controller can be configured to put the devices in active power-

down (CKE de-assertion with open pages) or pre-charge power-down (CKE de-

Desktop 4th Generation Intel

®

 Core

™

 Processor Family, Desktop Intel

®

 Pentium

®

 Processor Family, and Desktop Intel

®

 Celeron

®

Processor Family

Datasheet – Volume 1 of 2

July 2014

62

Order No.: 328897-009