Intel i3-4360T CM8064601481958 User Manual

Code execution is halted in C1 or deeper C-states. Package temperature can still be

monitored through PECI in lower C-states.

Unlike traditional thermal devices, the DTS outputs a temperature relative to the

maximum supported operating temperature of the processor (Tj

MAX

), regardless of

TCC activation offset. It is the responsibility of software to convert the relative

temperature to an absolute temperature. The absolute reference temperature is

readable in the TEMPERATURE_TARGET MSR 1A2h. The temperature returned by the

DTS is an implied negative integer indicating the relative offset from Tj

MAX

. The DTS

does not report temperatures greater than Tj

MAX

. The DTS-relative temperature

readout directly impacts the Adaptive Thermal Monitor trigger point. When a package

DTS indicates that it has reached the TCC activation (a reading of 0h, except when the

TCC activation offset is changed), the TCC will activate and indicate an Adaptive

Thermal Monitor event. A TCC activation will lower both IA core and graphics core

frequency, voltage, or both. Changes to the temperature can be detected using two

programmable thresholds located in the processor thermal MSRs. These thresholds

have the capability of generating interrupts using the core's local APIC. Refer to the

 64 and IA-32 Architectures Software Developer’s Manual for specific register

and programming details.

The error associated with DTS measurements will not exceed ±5 °C within the entire

operating range.

Intel Turbo Boost Technology allows processor cores and integrated graphics cores to

run faster than the baseline frequency. During a turbo event, the processor can

exceed its TDP power for brief periods. Turbo is invoked opportunistically and

automatically as long as the processor is conforming to its temperature, power

delivery, and current specification limits. Thus, thermal solutions and platform cooling

that are designed to less than thermal design guidance may experience thermal and

performance issues since more applications will tend to run at or near the maximum

power limit for significant periods of time.

Package processor core and internal graphics core powers are self monitored and

correspondingly reported out.
•

With the processor turbo disabled, rolling average power over 5 seconds will not

exceed the TDP rating of the part for typical applications.

•

on page 84)

— For the PL1: Package rolling average of the power set in POWER_LIMIT_1

(TURBO_POWER_LIMIT MSR 0610h bits [14:0]) over time window set in

POWER_LIMIT_1_TIME (TURBO_POWER_LIMIT MSR 0610h bits [23:17]) must

be less than or equal to the TDP package power as read from the

PACKAGE_POWER_SKU MSR 0614h for typical applications. Power control is

valid only when the processor is operating in turbo. PL1 lower than the

package TDP is not guaranteed.

— For the PL2: Package power will be controlled to a value set in

POWER_LIMIT_2 (TURBO_POWER_LIMIT MSR 0610h bits [46:32]). Occasional

brief power excursions may occur for periods of less than 10 ms over PL2.

Desktop 4th Generation Intel

®

 Core

™

 Processor Family, Desktop Intel

®

 Pentium

®

 Processor Family, and Desktop Intel

®

 Celeron

®

Processor Family

Datasheet – Volume 1 of 2

July 2014

82

Order No.: 328897-009