Intel i3-4360T CM8064601481958 User Manual

BCLKP
BCLKN

Differential bus clock input to the processor

I

Diff Clk

DPLL_REF_CLKP
DPLL_REF_CLKN

Embedded Display Port PLL Differential Clock In:

135 MHz

I

Diff Clk

SSC_DPLL_REF_CLKP
SSC_ DPLL_REF_CLKN

Spread Spectrum Embedded DisplayPort PLL

Differential Clock In: 135 MHz

I

Diff Clk

BPM#[7:0]

Outputs from the processor that indicate the status of

breakpoints and programmable counters used for

monitoring processor performance.

I/O

GTL

DBR#

Debug Reset: This signal is used only in systems where

no debug port is implemented on the system board.

DBR# is used by a debug port interposer so that an in-

target probe can drive system reset.

O

PRDY#

Processor Ready: This signal is a processor output

used by debug tools to determine processor debug

readiness.

O

GTL

PREQ#

Processor Request: This signal is used by debug tools

to request debug operation of the processor.

I

GTL

TCK

Test Clock: This signal provides the clock input for the

processor Test Bus (also known as the Test Access

Port). This signal must be driven low or allowed to float

during power on Reset.

I

GTL

TDI

Test Data In: This signal transfers serial test data into

the processor. This signal provides the serial input

needed for JTAG specification support.

I

GTL

TDO

Test Data Out: This signal transfers serial test data out

of the processor. This signal provides the serial output

needed for JTAG specification support.

O

Open Drain

TMS

Test Mode Select: This is a JTAG specification

supported signal used by debug tools.

I

GTL

TRST#

Test Reset: This signal resets the Test Access Port

(TAP) logic. This signal must be driven low during power

on Reset.

I

GTL

Desktop 4th Generation Intel

®

 Core

™

 Processor Family, Desktop Intel

®

 Pentium

®

 Processor Family, and Desktop Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 328897-009

91