Intel Xeon 5130 2.0GHz 124716 Data Sheet

30

Dual-Core Intel

® 

Xeon

® 

Processor 5100 Series Datasheet

1.

Unless otherwise noted, all specifications in this table apply to all processors and are based on estimates 

and simulations, not empirical data. These specifications will be updated with characterized data from 

silicon measurements at a later date.

2.

These voltages are targets only. A variable voltage source should exist on systems in the event that a 

different voltage is required. See 

 for more information. 

3.

The voltage specification requirements are measured across the VCC_DIE_SENSE and VSS_DIE_SENSE 

lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands with an oscilloscope set to 100 MHz 

bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of 

ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled 

in the scope probe. 

4.

The processor must not be subjected to any static V

CC

 level that exceeds the V

CC_MAX

 associated with any 

particular current. Failure to adhere to this specification can shorten processor lifetime.

5.

I

CC_MAX

 specification is based on maximum V

CC 

loadline The processor is capable of drawing I

CC_MAX 

for up 

to 10 ms. 

6.

I

CC_RESET

 is specified while PWRGOOD and RESET# are asserted. 

7.

This specification represents the total current for GTLREF_DATA and GTLREF_ADD.

8.

V

TT

 must be provided via a separate voltage source and must not be connected to V

CC

. This specification is 

measured at the land.

9.

Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE) 

shown in 

.

10. This specification refers to the total reduction of the load line due to VID transitions below the specified 

VID.

11. Individual processor VID values may be calibrated during manufacturing such that two devices at the same 

frequency may have different VID settings.

12. This specification applies to the VCCPLL land.

13. Baseboard bandwidth is limited to 20 MHz.

I

TT

I

CC

 for V

TT

 supply before V

CC

 

stable
I

CC

 for V

TT

 supply after V

CC

 

stable

4.5

4.6

A

16

I

CC_TDC

Thermal Design Current 

(TDC) Dual-Core Intel® 

Xeon® Processor LV 5148/

5138/5128

35

A

6,15

I

CC_TDC

Thermal Design Current 

(TDC) Dual-Core Intel

® 

Xeon

® 

Processor 5100 

Series

60

A

6,15

I

CC_TDC

Thermal Design Current 

(TDC) Dual-Core Intel® 

Xeon® Processor 5160

70

A

6,15

I

CC_VTT_OUT

DC current that may be 

drawn from V

TT_OUT 

per land 

580

mA

17

I

CC_GTLREF

I

CC

 for 

GTLREF_DATA and 

GTLREF_ADD 

200

µA

8

I

CC_VCCPLL

I

CC

 for PLL supply

130

mA

13

I

TCC

I

CC 

for Dual-Core Intel® 

Xeon® Processor LV 5148/

5138/5128 during active 

thermal control circuit (TCC)

45

A

I

TCC

I

CC 

for Dual-Core Intel

® 

Xeon

® 

Processor 5100 

Series during active thermal 

control circuit (TCC)

65

A

I

TCC

I

CC 

for Dual-Core Intel® 

Xeon® Processor 5160 

during active thermal control 

circuit (TCC)

90

A