Intel Quad-core Intel Xeon DP L5320 Passive BX80563L5320P Data Sheet

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

27

1.

V

TT 

supplies the PECI interface. PECI behavior does not affect V

TT

 min/max specifications.

2.

The leakage specification applies to powered devices on the PECI bus.

3.

One node is counted for each client and one node for the system host. Extended trace lengths might appear 

as additional nodes.

The input buffers in both client and host models must use a Schmitt-triggered input 
design for improved noise immunity. Use 

 as a guide for input buffer design.

Intel supports and validates dual processor configurations only in which both 
processors operate with the same FSB frequency, core frequency, number of cores, and 
have the same internal cache sizes. Mixing components operating at different internal 
clock frequencies is not supported and will not be validated by Intel. Combining 
processors from different power segments is also not supported.

V

p

Positive-edge threshold 

voltage

0.550 * V

TT

0.725 * V

TT

V

I

source

High level output source

(V

OH

 = 0.75 * V

TT

)

-6.0

N/A

mA

I

sink

Low level output sink

(V

OL

 = 0.25 * V

TT

)

0.5

1.0

mA

I

leak+

High impedance state 

leakage to V

TT

 

(V

leak

 = V

OL

) 

N/A

50

µA

2

I

leak-

High impedance leakage 

to GND 

(V

leak

 = V

OH

)

N/A

10

µA

2

C

bus

Bus capacitance per node

N/A

10

pF

3

V

noise

Signal noise immunity 

above 300 MHz

0.1 * V

TT

N/A

V

p-p

Minimum V

P

Maximum V

P

Minimum V

N

Maximum V

N

PECI High Range

PECI Low Range

Valid Input
Signal Range

Minimum
Hysteresis

V

TT

PECI Ground