Intel Quad-core Intel Xeon DP L5320 Passive BX80563L5320P Data Sheet

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

29

The processor DC specifications in this section are defined at the processor die 
(pads) unless noted otherwise. See 

 for the Quad-Core Intel® Xeon® 

Processor 5300 Series land listings and 

 for signal definitions. Voltage and 

current specifications are detailed in 

. For platform planning refer to 

, which provides V

CC

 Static and Transient Tolerances. This same information 

is presented graphically in 

The FSB clock signal group is detailed in 

. The DC specifications for the 

AGTL+ signals are listed in 

. Legacy signals and Test Access Port (TAP) 

signals follow DC specifications similar to GTL+. The DC specifications for the 
PWRGOOD input and TAP signal group are listed in 

 through 

 list the DC specifications for the processor and are valid 

only while meeting specifications for case temperature (T

CASE

 as specified in 

clock frequency, and input voltages. Care should be taken to read all notes associated 
with each parameter. 

The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the 
Quad-Core Intel® Xeon® Processor 5300 Series will have over certain time periods. 
The values are only estimates and actual specifications for future processors may differ. 
Processors may or may not have specifications equal to the FMB value in the 
foreseeable future. System designers should meet the FMB values to ensure their 
systems will be compatible with future processors.

VID

VID range for Quad-Core Intel® 

Xeon® Processor E5300 , Quad-

Core Intel® Xeon® Processor 

X5300 Series, and Quad-Core 

Intel® Xeon® Processor X5365 

Series

1.0000

1.5000

V

VID

VID Range for Quad-Core Intel® 

Xeon® Processor L5300 Series

1.1000

1.2500

V

VID

VID Range for Quad-Core Intel® 

Xeon® Processor L5318

0.9000

1.2500

V

V

CC

V

CC

 for processor core

Launch - FMB

See 

,

 and 

V

2, 3, 4, 6, 9

V

CC

_

BOOT

Default V

CC

 Voltage for initial power 

up

1.10

V

2

V

VID_STEP

VID step size during a transition

± 12.5

mV

V

VID_SHIFT

Total allowable DC load line shift 

from VID steps

450

mV

10

V

TT

FSB termination voltage (DC + AC 

specification)

1.14

1.20

1.26

V

8,13

V

CCPLL

PLL supply voltage (DC + AC 

specification)

1.455

1.500

1.605

V

I

CC

ICC for Quad-Core Intel® Xeon® 

Processor E5300  core with multiple 

VID
Launch - FMB

90

A

4,5,6,9