HGST HCS5C3232SLA380 User Manual
HITACHI CinemaStar 5K 320 Hard Disk Drive specification (Rev 1.21)
37
8.0
Registers
In Serial ATA, the host adapter contains a set of registers that shadow the contents of the traditional device
registers, referred to as the Shadow Register Block. Shadow Register Block registers are interface registers
used for delivering commands to the device or posting status from the device. About details, please refer to the
Serial ATA Specification.
In the following cases, the host adapter sets the BSY bit in its shadow Status Register and transmits a FIS to the
device containing the new contents.
Command register is written in the Shadow Register Block
Device Control register is written in the Shadow Register Block with a change of state of the SRST bit
COMRESET is requested
registers, referred to as the Shadow Register Block. Shadow Register Block registers are interface registers
used for delivering commands to the device or posting status from the device. About details, please refer to the
Serial ATA Specification.
In the following cases, the host adapter sets the BSY bit in its shadow Status Register and transmits a FIS to the
device containing the new contents.
Command register is written in the Shadow Register Block
Device Control register is written in the Shadow Register Block with a change of state of the SRST bit
COMRESET is requested
8.1 Alternate Status Register
Alternate Status Register
7
6
5
4
3
2
1
0
BSY
RDY
DF
DSC
/SERV
DRQ
COR
IDX
ERR
Table 23 Alternate Status Register
This register contains the same information as the Status Register. The only difference is that reading this
register does not imply interrupt acknowledge or clear a pending interrupt. See 8.13 "Status Register" on the
page 43 for the definition of the bits in this register.
register does not imply interrupt acknowledge or clear a pending interrupt. See 8.13 "Status Register" on the
page 43 for the definition of the bits in this register.
8.2 Command register
This register contains the command code being sent to the device. Command execution begins immediately
after this register is written. The command set is shown in Table 62 Command Set on page 95.
after this register is written. The command set is shown in Table 62 Command Set on page 95.
All other registers required for the command must be set up before writing the Command Register.
8.3 Cylinder High Register
This register contains the high order bits of the starting cylinder address for any disk access. At the end of the
command, this register is updated to reflect the current cylinder number.
command, this register is updated to reflect the current cylinder number.
In LBA Mode this register contains Bits 16-23. At the end of the command, this register is updated to reflect the
current LBA Bits 16-23.
current LBA Bits 16-23.
The cylinder number may be from zero to the number of cylinders minus one.
When 48-bit addressing commands are used, the "most recently written" content contains LBA Bits 16-23, and
the "previous content" contains Bits 40-47. The 48-bit Address feature set is described in 9.15.
the "previous content" contains Bits 40-47. The 48-bit Address feature set is described in 9.15.
8.4 Cylinder Low Register
This register contains the low order bits of the starting cylinder address for any disk access. At the end of the
command, this register is updated to reflect the current cylinder number.
command, this register is updated to reflect the current cylinder number.