HGST HCS5C3232SLA380 User Manual
HITACHI CinemaStar 5K 320 Hard Disk Drive specification (Rev 1.21)
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In LBA Mode this register contains Bits 8-15. At the end of the command, this register is updated to reflect the
current LBA Bits 8-15.
current LBA Bits 8-15.
The cylinder number may be from zero to the number of cylinders minus one.
When 48-bit addressing commands are used, the "most recently written" content contains LBA Bits 8-15, and
the "previous content" contains Bits 32-39.
the "previous content" contains Bits 32-39.
8.5 Data Register
This register is used to transfer data blocks between the device data buffer and the host. It is also the register
through which sector information is transferred on a Format Track command, and configuration information is
transferred on an Identify Device command.
through which sector information is transferred on a Format Track command, and configuration information is
transferred on an Identify Device command.
All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers are PIO
only.
only.
The register contains valid data only when DRQ=1 in the Status Register.
8.6 Device Control Register
Device Control Register
7
6
5
4
3
2
1
0
HOB
-
-
-
1
SRST
-IEN
0
Table 24 Device Control Register
Bit Definitions
HOB
HOB (high order byte) is defined by the 48-bit Address feature set. A write to
any Command Register shall clear the HOB bit to zero.
any Command Register shall clear the HOB bit to zero.
SRST (RST)
Software Reset. The device is held reset when RST=1. Setting RST=0
reenables the device.
reenables the device.
The host must set RST=1 and wait for at least 5 microseconds before setting
RST=0, to ensure that the device recognizes the reset.
RST=0, to ensure that the device recognizes the reset.
-IEN
Interrupt Enable. When -IEN=0, and the device is selected, device interrupts to
the host will be enabled. When -IEN=1, or the device is not selected, device
interrupts to the host will be disabled.
the host will be enabled. When -IEN=1, or the device is not selected, device
interrupts to the host will be disabled.
8.7 Drive Address Register
Drive Address Register
7
6
5
4
3
2
1
0
HIZ
-WTG
-H3
-H2
-H1
-H0
-DS1
-DS0
Table 25 Drive Address Register
This register contains the inverted drive select and head select addresses of the currently selected drive.