DELL 2 x Intel Xeon E7-4860 338-BFMX User Manual
Product codes
338-BFMX
Datasheet Volume 2 of 2
15
Intel Xeon Processor E7-8800/4800/2800 Product Families Architecture
2.2
Intel Xeon Processor E7-8800/4800/2800
Product Families Components (Boxes)
The Intel Xeon Processor E7-8800/4800/2800 Product Families consist of ten Intel Xeon
Processor E7-8800/4800/2800 Product Families cores connected to a shared, 30-MB
inclusive, 30-way set-associative Last-Level Cache (LLC) by a high-bandwidth
interconnect. The cores and shared LLC are connected via caching agents (Cbox) and
system interface (Sbox) to the Intel QuickPath Interconnect router (Rbox), the on-chip
Intel QuickPath Interconnect home agents and memory controllers (Bboxes + Mboxes),
and the system configuration agent (Ubox). The Rbox is a general-purpose Intel
QuickPath Interconnect router that connects cores to the Bboxes, the four external
Intel QuickPath Interconnects (through the pad controllers, or Pboxes), and the system
configuration agent (Ubox), through the Sboxes. The Ubox shares an Rbox port with
one of the Bboxes.
Processor E7-8800/4800/2800 Product Families cores connected to a shared, 30-MB
inclusive, 30-way set-associative Last-Level Cache (LLC) by a high-bandwidth
interconnect. The cores and shared LLC are connected via caching agents (Cbox) and
system interface (Sbox) to the Intel QuickPath Interconnect router (Rbox), the on-chip
Intel QuickPath Interconnect home agents and memory controllers (Bboxes + Mboxes),
and the system configuration agent (Ubox). The Rbox is a general-purpose Intel
QuickPath Interconnect router that connects cores to the Bboxes, the four external
Intel QuickPath Interconnects (through the pad controllers, or Pboxes), and the system
configuration agent (Ubox), through the Sboxes. The Ubox shares an Rbox port with
one of the Bboxes.
With respect to the Intel QuickPath Interconnect specification, Sboxes and Bboxes
collectively implement the Intel QuickPath Interconnect Protocol layer (caching agent
and home agent sides, respectively). The Rbox functions as both an Intel QuickPath
Interconnect Layer agent and an Intel QuickPath Interconnect Routing agent. The Ubox
is used as the Intel Xeon Processor E7-8800/4800/2800 Product Families Intel
QuickPath Interconnect Configuration Agent and participates in many of the non-
coherent Intel QuickPath Interconnect Protocol flows. The Intel QuickPath Interconnect
Physical layer is implemented by the Pbox.
collectively implement the Intel QuickPath Interconnect Protocol layer (caching agent
and home agent sides, respectively). The Rbox functions as both an Intel QuickPath
Interconnect Layer agent and an Intel QuickPath Interconnect Routing agent. The Ubox
is used as the Intel Xeon Processor E7-8800/4800/2800 Product Families Intel
QuickPath Interconnect Configuration Agent and participates in many of the non-
coherent Intel QuickPath Interconnect Protocol flows. The Intel QuickPath Interconnect
Physical layer is implemented by the Pbox.
Each core is connected to the un-core interconnect through a corresponding Caching
agent. The Cbox is both the interface to the core interconnect and a last-level cache
bank. The Cboxes can operate in parallel, processing core requests (reads, writes,
writebacks) and external snoops, and returning cached data and responses to the cores
and Intel QuickPath Interconnect system agents. The Intel Xeon Processor E7-8800/
4800/2800 Product Families implement a bypass path from the Sbox to the
corresponding Bbox to reduce the memory latency for requests targeting memory
addresses mapped by that Bbox. When configured in “hemisphere” mode, the Bbox will
only map addresses corresponding to the corresponding Sbox in this and other sockets.
If the system or applications are NUMA (non-uniform memory access) optimized, the
cores on this socket will mostly access the memory on this socket. Combining NUMA
optimizations and hemisphering results in most memory requests accessing the Bbox
that is directly connected to the requesting Sbox, minimizing memory latency.
agent. The Cbox is both the interface to the core interconnect and a last-level cache
bank. The Cboxes can operate in parallel, processing core requests (reads, writes,
writebacks) and external snoops, and returning cached data and responses to the cores
and Intel QuickPath Interconnect system agents. The Intel Xeon Processor E7-8800/
4800/2800 Product Families implement a bypass path from the Sbox to the
corresponding Bbox to reduce the memory latency for requests targeting memory
addresses mapped by that Bbox. When configured in “hemisphere” mode, the Bbox will
only map addresses corresponding to the corresponding Sbox in this and other sockets.
If the system or applications are NUMA (non-uniform memory access) optimized, the
cores on this socket will mostly access the memory on this socket. Combining NUMA
optimizations and hemisphering results in most memory requests accessing the Bbox
that is directly connected to the requesting Sbox, minimizing memory latency.
provides a Intel Xeon Processor E7-8800/4800/2800 Product Families block
diagram.