DELL 2 x Intel Xeon E7-4860 338-BFMX User Manual
Product codes
338-BFMX
Datasheet Volume 2 of 2
17
Address Map
3
Address Map
3.1
NodeID Generation
Intel Xeon processor 7500 series system addresses are made up of a socket and a
device within the socket. With a 5-bit NodeID in the Intel QuickPath Interconnect SMP
profile, Intel Xeon processor 7500 series can support up to four sockets (chosen by
NID[3:2] when NID[4] is zero). Within each socket are four devices (NID[1:0]): IOH
(00), B0/S0 (01), Ubox (10), B1/S1 (11). The IOH is the chipset; B0/S0 and B1/S1 are
two sets of home agents (Bboxes) and caching agents (Sboxes); the Ubox is the
configuration agent.
device within the socket. With a 5-bit NodeID in the Intel QuickPath Interconnect SMP
profile, Intel Xeon processor 7500 series can support up to four sockets (chosen by
NID[3:2] when NID[4] is zero). Within each socket are four devices (NID[1:0]): IOH
(00), B0/S0 (01), Ubox (10), B1/S1 (11). The IOH is the chipset; B0/S0 and B1/S1 are
two sets of home agents (Bboxes) and caching agents (Sboxes); the Ubox is the
configuration agent.
3.1.1
DRAM Decoder
There are four node assignment methods implemented for the DRAM Decoder. In each
method, three target list index bits are used to look up NID bits [4:1] from an 8-entry
4-bit target list. Two modes use mixed address bits (when tgtsel is 0). Two modes use
low-order address bits (when tgtsel is 1).
method, three target list index bits are used to look up NID bits [4:1] from an 8-entry
4-bit target list. Two modes use mixed address bits (when tgtsel is 0). Two modes use
low-order address bits (when tgtsel is 1).
shows which address bits are used
for the target list index, based on the value of tgtsel.
Based on the value of tgtidx[2:0], a four bit value listnid[4:1] is selected from
tgtlist[31:0] as follows:
tgtlist[31:0] as follows:
• listnid[4] = tgtlist[{tgtidx[2:0], 2b'11}]
• listnid[3] = tgtlist[{tgtidx[2:0], 2b'10}]
• listnid[2] = tgtlist[{tgtidx[2:0], 2b'01}]
• listnid[1] = tgtlist[{tgtidx[2:0], 2b'00}]
• listnid[3] = tgtlist[{tgtidx[2:0], 2b'10}]
• listnid[2] = tgtlist[{tgtidx[2:0], 2b'01}]
• listnid[1] = tgtlist[{tgtidx[2:0], 2b'00}]
The value of listnid[4:1] is used in conjunction with the hemisphere bit (cboxid[2]), and
idbase (from the array payload) to form NID[4:0] according to
idbase (from the array payload) to form NID[4:0] according to
. Note that
cboxid[2] is logically XOR'ed into this calculation in the implementation, so if listnid[1]
is not used in a particular mode, it should be set to zero in the payload.
is not used in a particular mode, it should be set to zero in the payload.
Using socket-level interleaving is known as "hemisphere mode". This requires that
Bboxes on the same socket have identical memory configurations. In this model, the
number of CAs which talk to a particular Bbox is reduced from 32 (in a four-socket
system) to 16. This allows each CAs to use up 48 tracker entries in each Bbox. In order
to use this model, external agents (that is, IOHs and XNCs) must understand how the
interleaving between "even" and "odd" Bboxes is done, which is generated from the
address by the Intel Xeon processor 7500 series hash function.
Bboxes on the same socket have identical memory configurations. In this model, the
number of CAs which talk to a particular Bbox is reduced from 32 (in a four-socket
system) to 16. This allows each CAs to use up 48 tracker entries in each Bbox. In order
to use this model, external agents (that is, IOHs and XNCs) must understand how the
interleaving between "even" and "odd" Bboxes is done, which is generated from the
address by the Intel Xeon processor 7500 series hash function.
Table 3-1.
Target List Index
Mode
tgtsel
tgtidx[2]
tgtidx[1]
tgtidx[0]
Mixed
0
addr[8] ^ addr[18]
addr[7] ^ addr[17]
addr[6] ^ addr[16]
Low-order
1
addr[8]
addr[7]
addr[6]
Table 3-2.
NodeID Formation
Mode
hemi
NID[4]
NID[3]
NID[2]
NID[1]
NID[0]
Home
0
listnid[4]
listnid[3]
listnid[2]
listnid[1]
idbase
Socket
1
listnid[4]
listnid[3]
listnid[2]
listnid[1] ^cboxid[3]
idbase