DELL 2 x Intel Xeon E7-4860 338-BFMX User Manual
Product codes
338-BFMX
Datasheet Volume 2 of 2
41
Power Management Architecture (Wbox)
referred to as ''C'' states. C0 refers to the processor active state, and all other C-states
are idle states. Higher numbered C-states are lower power, but longer latency. C3 is
lower power than C1, and so on.
are idle states. Higher numbered C-states are lower power, but longer latency. C3 is
lower power than C1, and so on.
States C0, C1 require that processor caches maintain coherence – in other words, they
must ensure that any memory requests from other system agents receive the latest
copy of the data if it is stored in the processors cache. The ACPI spec states that cache
coherency in states C3 and lower is the responsibility of the OS to maintain. However,
the entry flow of the Intel Xeon Processor E7-8800/4800/2800 Product Families core
into C3 state includes flushing of the core’s first level and mid-level caches into the
large last level cache. The last level cache remains available, snoopable, and coherent
even if all cores enter C3 state.
must ensure that any memory requests from other system agents receive the latest
copy of the data if it is stored in the processors cache. The ACPI spec states that cache
coherency in states C3 and lower is the responsibility of the OS to maintain. However,
the entry flow of the Intel Xeon Processor E7-8800/4800/2800 Product Families core
into C3 state includes flushing of the core’s first level and mid-level caches into the
large last level cache. The last level cache remains available, snoopable, and coherent
even if all cores enter C3 state.
ACPI also provides for power management of the system. ACPI S-states refer to the
execution state of the system. S0 is the system active state, and all other S-states are
system idle states. Within the S0 state, a given processor can be active (C0 state) or
idle (C1 or lower states). In all other S-states, the processor is inactive. Note that here
''inactive'' doesn't mean that the processor is any specific C-state – C-states are only
applicable while the system is in S0. As with processor C-states, the latency to enter
and exit an S-state and the power consumed in that state are inversely proportional.
execution state of the system. S0 is the system active state, and all other S-states are
system idle states. Within the S0 state, a given processor can be active (C0 state) or
idle (C1 or lower states). In all other S-states, the processor is inactive. Note that here
''inactive'' doesn't mean that the processor is any specific C-state – C-states are only
applicable while the system is in S0. As with processor C-states, the latency to enter
and exit an S-state and the power consumed in that state are inversely proportional.
9.2.2
C-State Support
The Intel Xeon processor E7-8800/4800/2800 Product Families will provide support for
C0, C1, C1E, C3, and C6. Note that the behavior in a particular C-state on Intel Xeon
Processor E7-8800/4800/2800 Product Families may be different than states referred
to with the same number on previous products. The platform change, including the
move to an Intel QuickPath Interconnect bus interface, results in the elimination of the
STPCLK#, SLP# signals, and as a result there is no need to support C2 type states on
the Intel Xeon Processor E7-8800/4800/2800 Product Families.
C0, C1, C1E, C3, and C6. Note that the behavior in a particular C-state on Intel Xeon
Processor E7-8800/4800/2800 Product Families may be different than states referred
to with the same number on previous products. The platform change, including the
move to an Intel QuickPath Interconnect bus interface, results in the elimination of the
STPCLK#, SLP# signals, and as a result there is no need to support C2 type states on
the Intel Xeon Processor E7-8800/4800/2800 Product Families.
9.2.2.1
Valid C-State Transitions
At an architectural level, a logical processor can only make direct transitions to and
from the C0 state. It cannot transition directly between any other C-states. For
example, a logical processor cannot transition directly from C1 to C3; it must go
through C0.
from the C0 state. It cannot transition directly between any other C-states. For
example, a logical processor cannot transition directly from C1 to C3; it must go
through C0.
Valid thread/core C-state transitions are shown in
. Note that the resolved
core C-state is the highest power (lowest numerical) C-state requested by any of the
threads present in that core.
threads present in that core.