Intel Pentium D 945 HH80553PG0964MN User Manual

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The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT 

state. If Enhanced HALT state is not enabled in the BIOS, the default Snoop State 

entered will be the HALT Snoop State. Refer to the following sections for details on 

HALT Snoop State, Grant Snoop State and Enhanced HALT Snoop State.

The processor will respond to snoop transactions on the FSB while in Stop-Grant state 

or in HALT Power Down state. During a snoop transaction, the processor enters the 

HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the 

snoop on the FSB has been serviced (whether by the processor or another agent on the 

FSB). After the snoop is serviced, the processor will return to the Stop Grant state or 

HALT Power Down state, as appropriate.

The Enhanced HALT Snoop State is the default Snoop State when the Enhanced HALT 

state is enabled via the BIOS. The processor will remain in the lower bus ratio and VID 

operating point of the Enhanced HALT state.
While in the Enhanced HALT Snoop State, snoops are handled the same way as in the 

HALT Snoop State. After the snoop is serviced the processor will return to the Enhanced 

HALT state.

Enhanced Intel SpeedStep

®

 technology enables the processor to switch between 

frequency and voltage points, which may result in platform power savings. To support 

this technology, the system must support dynamic VID transitions. Switching between 

voltage/frequency states is software controlled.

Not all processors are capable of supporting Enhanced Intel SpeedStep technology. 

More details on which processor frequencies will support this feature will be provided in 

future releases of the Intel

Processor Extreme Edition 955, 965 Specification Update.
Enhanced Intel SpeedStep technology is a technology that creates processor 

performance states (P states). P states are power consumption and capability states 

within the Normal state as shown in 

. Enhanced Intel SpeedStep technology 

enables real-time dynamic switching between frequency and voltage points. It alters 

the performance of the processor by changing the bus to core frequency ratio and 

voltage. This allows the processor to run at different core frequencies and voltages to 

best serve the performance and power requirements of the processor and system. Note 

that the front side bus is not altered; only the internal core frequency is changed. To 

run at reduced power consumption, the voltage is altered in step with the bus ratio. 
The following are key features of Enhanced Intel SpeedStep technology:

• Voltage/Frequency selection is software controlled by writing to processor MSRs 

(Model Specific Registers); thus, eliminating chipset dependency.

• If the target frequency is higher than the current frequency, Vcc is incriminated in 

steps (+12.5 mV) by placing a new value on the VID signals and the processor 

shifts to the new frequency. Note that the top frequency for the processor can not 

be exceeded.

• If the target frequency is lower than the current frequency, the processor shifts to 

the new frequency and V

CC

 is then decremented in steps (-12.5 mV) by changing 

the target VID through the VID signals.