AMD Athlon™ 64 X2 Dual-Core Processor 4200+ ADO4200DOBOX Data Sheet
Product codes
ADO4200DOBOX
Advanced Micro Devices
AMD Athlon™ 64 X2
Dual-Core Processor
Product Data Sheet
Dual-Core Processor
Product Data Sheet
•
Compatible with Existing 32-Bit Code Base
–
–
Including support for SSE, SSE2, SSE3
*
, MMX™,
3DNow!™ technology and legacy x86 instructions
*SSE3 supported by Rev E and later processors.
*SSE3 supported by Rev E and later processors.
–
Runs existing operating systems and drivers
–
Local APIC on-chip
•
AMD64 Technology
–
–
AMD64 technology instruction set extensions
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64-bit integer registers, 48-bit virtual addresses,
40-bit physical addresses
40-bit physical addresses
–
Eight additional 64-bit integer registers (16 total)
–
Eight additional 128-bit SSE/SSE2/SSE3 registers
(16 total)
(16 total)
•
Dual-Core Architecture
–
–
Discrete L1 and L2 cache structures for each core
•
HyperTransport™ Technology to I/O Devices
–
–
One 16-bit link supporting speeds up to 1 GHz (2000
MT/s) or 4 Gigabytes/s in each direction
MT/s) or 4 Gigabytes/s in each direction
•
64-Kbyte 2-Way Associative ECC-Protected
L1 Data Caches
–
L1 Data Caches
–
Two 64-bit operations per cycle, 3-cycle latency
•
64-Kbyte 2-Way Associative Parity-Protected
L1 Instruction Caches
–
L1 Instruction Caches
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With advanced branch prediction
•
16-Way Associative ECC-Protected
L2 Caches
–
L2 Caches
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Exclusive cache architecture—storage in addition
to L1 caches
to L1 caches
–
Up to 1 Mbyte per L2 cache
•
Machine Check Architecture
–
–
Includes hardware scrubbing of major
ECC-protected arrays
ECC-protected arrays
•
Power Management
–
–
Multiple low-power states including C1E*
*C1E supported by Rev. G or later processors.
*C1E supported by Rev. G or later processors.
–
System Management Mode (SMM)
–
ACPI-compliant, including support for processor
performance states
performance states
939-Pin Package Specific Features
•
Refer to the AMD Functional Data Sheet,
939-Pin Package, order# 31411, for functional,
electrical, and mechanical details of 939-pin
package processors.
939-Pin Package, order# 31411, for functional,
electrical, and mechanical details of 939-pin
package processors.
•
Electrical Interfaces
–
–
HyperTransport™ technology: LVDS-like
differential, unidirectional
differential, unidirectional
–
DDR SDRAM: SSTL_2 per JEDEC specification
–
Clock, reset, and test signals also use DDR
SDRAM-like electrical specifications
SDRAM-like electrical specifications
•
Packaging
–
–
939-pin lidded micro PGA
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1.27-mm pin pitch
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31x31-row pin array
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40mm x 40mm organic substrate
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Organic C4 die attach
•
Integrated Memory Controller
–
–
Low-latency, high-bandwidth
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144-bit DDR SDRAM at 100, 133, 166, and 200
MHz
MHz
–
Supports up to four unbuffered DIMMs
–
ECC checking with double-bit detect and single-bit
correct
correct
33425
Publication #
3.10
Revision:
January 2007
Issue Date: