Microchip Technology 25AA02E48T-I/OT Memory IC SOT-23-6 2 K 256 x 8 25AA02E48T-I/OT Data Sheet
Product codes
25AA02E48T-I/OT
2008-2013 Microchip Technology Inc.
DS20002123D-page 3
25AA02E48/25AA02E64
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C
V
CC
= 1.8V to 5.5V
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
1
F
CLK
Clock Frequency
—
—
—
—
—
10
5
3
3
MHz
MHz
MHz
MHz
MHz
4.5V
V
CC
5.5V
2.5V
V
CC
4.5V
1.8V
V
CC
2.5V
2
T
CSS
CS Setup Time
50
100
150
150
—
—
—
—
—
ns
ns
ns
ns
ns
4.5V
V
CC
5.5V
2.5V
V
CC
4.5V
1.8V
V
CC
2.5V
3
T
CSH
CS Hold Time
100
200
250
200
250
—
—
—
—
—
ns
ns
ns
ns
ns
4.5V
V
CC
5.5V
2.5V
V
CC
4.5V
1.8V
V
CC
2.5V
4
T
CSD
CS Disable Time
50
—
ns
—
5
Tsu
Data Setup Time
10
20
30
20
30
—
—
—
—
—
ns
ns
ns
ns
ns
4.5V
V
CC
5.5V
2.5V
V
CC
4.5V
1.8V
V
CC
2.5V
6
T
HD
Data Hold Time
20
40
50
40
50
—
—
—
—
—
ns
ns
ns
ns
ns
4.5V
V
CC
5.5V
2.5V
V
CC
4.5V
1.8V
V
CC
2.5V
7
T
R
CLK Rise Time
—
100
ns
(
)
8
T
F
CLK Fall Time
—
100
ns
(
)
9
T
HI
Clock High Time
50
100
150
150
—
—
—
—
—
ns
ns
ns
ns
ns
4.5V
V
CC
5.5V
2.5V
V
CC
4.5V
1.8V
V
CC
2.5V
10
T
LO
Clock Low Time
50
100
150
150
—
—
—
—
—
ns
ns
ns
ns
ns
4.5V
V
CC
5.5V
2.5V
V
CC
4.5V
1.8V
V
CC
2.5V
11
T
CLD
Clock Delay Time
50
—
ns
—
12
T
CLE
Clock Enable Time
50
—
ns
—
13
T
V
Output Valid from Clock
Low
Low
—
—
—
—
—
50
100
160
160
ns
ns
ns
ns
ns
4.5V
V
CC
5.5V
2.5V
V
CC
4.5V
1.8V
V
CC
2.5V
14
T
HO
Output Hold Time
0
—
ns
(
)
15
T
DIS
Output Disable Time
—
—
—
—
—
40
80
80
160
ns
ns
ns
ns
ns
4.5V
V
CC
5.5V (
)
2.5V
V
CC
4.5V (
)
1.8V
V
CC
2.5V (
)
16
T
HS
HOLD Setup Time
20
40
80
40
80
—
—
—
—
—
ns
ns
ns
ns
ns
4.5V
V
CC
5.5V
2.5V
V
CC
4.5V
1.8V
V
CC
2.5V
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.Microchip.com.
at www.Microchip.com.
3: T
WC
begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.