Microchip Technology IC MCU OTP 4K PIC16C74B-20/L PLCC-44 MCP PIC16C74B-20/L Data Sheet

Product codes
PIC16C74B-20/L
Page of 186
 1998-2013 Microchip Technology Inc.
DS30605D-page 27
PIC16C63A/65B/73B/74B
4.5
Indirect Addressing, INDF and 
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing. 
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = '0') will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-4.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
EXAMPLE 4-2:
INDIRECT ADDRESSING
movlw
0x20
;initialize pointer
movwf
FSR
;to RAM
NEXT
clrf
INDF
;clear INDF register
incf
FSR,F
;inc pointer
btfss
FSR,4
;all done? 
goto
NEXT
;no clear next
CONTINUE
:
;yes continue
 
FIGURE 4-4:
DIRECT/INDIRECT ADDRESSING
Note:
Maintain the IRP and RP1 bits clear.
Note 1: For register file map detail, see Figure 4-2.
2: Shaded portions are not implemented; maintain the IRP and RP1 bits clear.
Data
Memory
Indirect Addressing
Direct Addressing
bank select
location select
RP1:RP0
6
0
from opcode
IRP
FSR register
7
0
bank select
location select
00
01
10
11
Bank 0
Bank 1
Bank 2
Bank 3
not used
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
0
0