Microchip Technology IC PIC MCU PIC16F1937-I/PT TQFP-44 MCP PIC16F1937-I/PT Data Sheet
Product codes
PIC16F1937-I/PT
2008-2011 Microchip Technology Inc.
DS41364E-page 243
PIC16(L)F1934/6/7
FIGURE 24-4:
SPI MASTER AND MULTIPLE SLAVE CONNECTION
24.2.1
SPI MODE REGISTERS
The MSSP module has five registers for SPI mode
operation. These are:
• MSSP STATUS register (SSPSTAT)
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 3 (SSPCON3)
• MSSP Data Buffer register (SSPBUF)
• MSSP Address register (SSPADD)
• MSSP Shift register (SSPSR)
operation. These are:
• MSSP STATUS register (SSPSTAT)
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 3 (SSPCON3)
• MSSP Data Buffer register (SSPBUF)
• MSSP Address register (SSPADD)
• MSSP Shift register (SSPSR)
(Not directly accessible)
SSPCON1 and SSPSTAT are the control and STATUS
registers in SPI mode operation. The SSPCON1 regis-
ter is readable and writable. The lower 6 bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
In one SPI master mode, SSPADD can be loaded with
a value used in the Baud Rate Generator. More infor-
mation on the Baud Rate Generator is available in
registers in SPI mode operation. The SSPCON1 regis-
ter is readable and writable. The lower 6 bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
In one SPI master mode, SSPADD can be loaded with
a value used in the Baud Rate Generator. More infor-
mation on the Baud Rate Generator is available in
SSPSR is the shift register used for shifting data in and
out. SSPBUF provides indirect access to the SSPSR
register. SSPBUF is the buffer register to which data
bytes are written, and from which data bytes are read.
In receive operations, SSPSR and SSPBUF together
create a buffered receiver. When SSPSR receives a
complete byte, it is transferred to SSPBUF and the
SSPIF interrupt is set.
During transmission, the SSPBUF is not buffered. A
write to SSPBUF will write to both SSPBUF and
SSPSR.
out. SSPBUF provides indirect access to the SSPSR
register. SSPBUF is the buffer register to which data
bytes are written, and from which data bytes are read.
In receive operations, SSPSR and SSPBUF together
create a buffered receiver. When SSPSR receives a
complete byte, it is transferred to SSPBUF and the
SSPIF interrupt is set.
During transmission, the SSPBUF is not buffered. A
write to SSPBUF will write to both SSPBUF and
SSPSR.
SPI Master
SCK
SDO
SDI
General I/O
General I/O
General I/O
General I/O
General I/O
SCK
SDI
SDO
SS
SDI
SDO
SS
SPI Slave
#1
SCK
SDI
SDO
SS
SDI
SDO
SS
SPI Slave
#2
SCK
SDI
SDO
SS
SDI
SDO
SS
SPI Slave
#3