Microchip Technology IC PIC MCU PIC16F1937-I/PT TQFP-44 MCP PIC16F1937-I/PT Data Sheet

 2008-2011 Microchip Technology Inc.

DS41364E-page 273

24.6.5

I

2

C MASTER MODE REPEATED 

START CONDITION TIMING

A Repeated Start condition occurs when the RSEN bit
of the SSPCON2 register is programmed high and the
Master state machine is no longer active. When the
RSEN bit is set, the SCL pin is asserted low. When the
SCL pin is sampled low, the Baud Rate Generator is
loaded and begins counting. The SDA pin is released
(brought high) for one Baud Rate Generator count
(T

BRG

). When the Baud Rate Generator times out, if

SDA is sampled high, the SCL pin will be deasserted
(brought high). When SCL is sampled high, the Baud
Rate Generator is reloaded and begins counting. SDA
and SCL must be sampled high for one T

BRG

. This

action is then followed by assertion of the SDA pin
(SDA = 0) for one T

BRG

 while SCL is high. SCL is

asserted low. Following this, the RSEN bit of the

SSPCON2 register will be automatically cleared and
the Baud Rate Generator will not be reloaded, leaving
the SDA pin held low. As soon as a Start condition is
detected on the SDA and SCL pins, the S bit of the
SSPSTAT register will be set. The SSPIF bit will not be
set until the Baud Rate Generator has timed out.

If RSEN is programmed while any other
event is in progress, it will not take effect.

A bus collision during the Repeated Start
condition occurs if: 

• SDA is sampled low when SCL 

goes from low-to-high.

• SCL goes low before SDA is 

asserted low. This may indicate 
that another master is attempting to 
transmit a data ‘1’. 

SDA

SCL

Repeated Start

Write to SSPCON2 

Write to SSPBUF occurs here

At completion of Start bit, 
hardware clears RSEN bit

1st bit

S bit set by hardware

T

BRG

T

BRG

SDA = 1,

SDA = 1, 

SCL (no change)

SCL = 1

occurs here

T

BRG

T

BRG

T

BRG

     and sets SSPIF

Sr