Texas Instruments Single Cell Battery Fuel Gauge Evaluation Module BQ27210EVM BQ27210EVM Data Sheet
Product codes
BQ27210EVM
www.ti.com
Taper Current (TAPER) — Address 0x7B
Pack Configuration (PKCFG) — Address 0x7C
SLUS707B – APRIL 2006 – REVISED JANUARY 2007
This register contains the enable bit for the capacity aging estimate and the charge taper current value. The
taper current value, in addition to battery voltage, is used to determine when the battery has reached a full
charge state. The equation for programming the taper current is:
taper current value, in addition to battery voltage, is used to determine when the battery has reached a full
charge state. The equation for programming the taper current is:
TAPER[6-0] = Design Taper Current (mA) * R
S
(m
Ω
) / 228 µV
where R
S
is the value of the sense resistor used in the system.
TAPER[7] should be set to 1 to enable the automatic aging of the LMD full capacity value when there are no
learning cycles. If this feature is enabled, LMD is reduced by Design Capacity / 1024 every time CYCL
increments by 2 and every time that a cumulative NAC self-discharge estimate reduction of 1.56% has been
made without charging the battery to full. If TAPER[7] is set to 0, there is no LMD reduction with cycle count or
self-discharge.
learning cycles. If this feature is enabled, LMD is reduced by Design Capacity / 1024 every time CYCL
increments by 2 and every time that a cumulative NAC self-discharge estimate reduction of 1.56% has been
made without charging the battery to full. If TAPER[7] is set to 0, there is no LMD reduction with cycle count or
self-discharge.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME
GPIEN
QV1
QV0
BOFF(2)
BOFF(1)
BOFF(0)
DCFIX
TCFIX
GPIEN
Allows the pack manufacturer to set the state of the GPIO pin on initial power up. If the bit is 0, the
GPIEN bit is cleared on reset and the GPIO pin acts as a high-impedance output. If the bit is 1, the
GPIEN bit is set on reset and the GPIO pin acts as an input. The state of the GPIO pin can then be
read through the GPSTAT bit in the MODE register. If PKCFG is updated using the UPCFG host
command (see Device Control section), the updated PKCFG value will not reinitialize GPIEN in the
MODE register.
GPIEN bit is cleared on reset and the GPIO pin acts as a high-impedance output. If the bit is 1, the
GPIEN bit is set on reset and the GPIO pin acts as an input. The state of the GPIO pin can then be
read through the GPSTAT bit in the MODE register. If PKCFG is updated using the UPCFG host
command (see Device Control section), the updated PKCFG value will not reinitialize GPIEN in the
MODE register.
QV1 & QV0 These bits set the minimum qualification voltage for charge termination. The termination voltage
thresholds are set as listed in
Table 3. Charge Termination Voltage Settings
QV1
QV0
Voltage (mV)
0
0
3968
0
1
4016
1
0
4064
1
1
4112
BOFF
These bits are used to store a typical board offset value for the gauge. This value is added to the
internal offset measurement and the total applied as an offset correction for the charge and
discharge coulometric measurements made by the DSCC. This is a 2s-complement signed number
with a value of 2.45 µV per bit.
internal offset measurement and the total applied as an offset correction for the charge and
discharge coulometric measurements made by the DSCC. This is a 2s-complement signed number
with a value of 2.45 µV per bit.
Table 4. Board Offset Voltage Settings
Board Offset
BOFF(2)
BOFF(1)
BOFF(0)
7.35 µV
0
1
1
4.9 µV
0
1
0
2.45 µV
0
0
1
0
0
0
0
-2.45 µV
1
1
1
-4.9 µV
1
1
0
-7.35 µV
1
0
1
-9.8 µV
1
0
0
20