Microchip Technology IC MCU 8BIT PIC18F65K22-I/PT TQFP-64 MCP PIC18F65K22-I/PT Data Sheet
Product codes
PIC18F65K22-I/PT
2009-2011 Microchip Technology Inc.
DS39960D-page 205
PIC18F87K22 FAMILY
14.8.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full cycle length of a Timer1
gate signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. (For timing details, see
possible to measure the full cycle length of a Timer1
gate signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. (For timing details, see
.)
The T1GVAL bit (T1GCON<2>) indicates when the
Toggled mode is active and the timer is counting.
The Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit (T1GCON<5>). When T1GTM is cleared,
the flip-flop is cleared and held clear. This is necessary
in order to control which edge is measured.
Toggled mode is active and the timer is counting.
The Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit (T1GCON<5>). When T1GTM is cleared,
the flip-flop is cleared and held clear. This is necessary
in order to control which edge is measured.
FIGURE 14-5:
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
Timer1
N
N + 1 N + 2 N + 3
N + 4
N + 5 N + 6 N + 7
N + 8